The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in BF2 implanted P+ gate P-channel MOSFETs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1990, Pages 111-112

  Tseng, Hsing Huang ^a   Tobin, Philip J ^a   Baker, Frank K ^a   Pfiester, James R ^a   Evans, Keenan ^b   Fejes, Peter ^c  

^a MOTOROLA INC   (United States)

^b Discrete Semiconductor Technologies Group ^*  (United States)

^c Advanced Systems Research Laboratory   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS SI; BORON DIFFUSIONS; BORON PENETRATION; CO-IMPLANT; FLUORINE DIFFUSION; GATE ELECTRODES; GATE OXIDE; GATE OXIDE PROCESS; GRAIN SIZE; INTERFACE TRAP DENSITY; MOSFETS; POLY GATES; SI SUBSTRATES; STRONG INTERACTION; THIN OXIDES; TRAP GENERATION; TUNGSTEN POLYCIDE; VOLTAGE INSTABILITY;

AMORPHOUS FILMS; AMORPHOUS SILICON; BORON; DEPOSITS; DIFFUSION IN SOLIDS; ELECTRON TRAPS; FLUORINE; GATES (TRANSISTOR); GRAIN BOUNDARIES; GRAIN SIZE AND SHAPE; MICROSTRUCTURE; SILICON; SEMICONDUCTING SILICON;

MOSFET DEVICES; SEMICONDUCTOR DEVICES, MOSFET;

DIGEST OF PAPER; P-CHANNEL MOSFET;

EID: 0025591291     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.1990.111033     Document Type: Conference Paper

References (5)

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