An embedded microprocessor radiation hardened by microarchitecture and circuits

IEEE Transactions on Computers

Volumn 65, Issue 2, 2016, Pages 382-395

  Clark, Lawrence T ^a   Patterson, Dan W ^a   Ramamurthy, Chandarasekaran ^a   Holbert, Keith E ^a  

^a Arizona State University   (United States)

Author keywords

cache memory; microprocessor; Radiation hardening by design (RHBD); single event transients; single event effects; soft error mitigation; total ionizing dose

Indexed keywords

BUFFER STORAGE; CACHE MEMORY; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; DESIGN; ERROR CORRECTION; ERRORS; FLIP FLOP CIRCUITS; HARDENING; HIGH ELECTRON MOBILITY TRANSISTORS; INTEGRATED CIRCUIT DESIGN; IONIZING RADIATION; MICROPROCESSOR CHIPS; PIPELINES; RADIATION EFFECTS; RECONFIGURABLE HARDWARE; TRANSIENTS;

RADIATION HARDENING BY DESIGN; SINGLE EVENT EFFECTS; SINGLE EVENT TRANSIENTS; SOFT ERROR MITIGATIONS; TOTAL IONIZING DOSE;

RADIATION HARDENING;

EID: 84962050596     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2015.2419661     Document Type: Article

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