A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 256-257

  Ditlow, Gary S ^a   Montoye, Robert K ^a   Storino, Salvatore N ^b   Dance, Sherman M ^b   Ehrenreich, Sebastian ^c   Fleischer, Bruce M ^a   Fox, Thomas W ^a   Holmes, Kyle M ^b   Mihara, Junichi ^d   Nakamura, Yutaka ^d   Onishi, Shohji ^d   Shearer, Robert ^b   Wendel, Dieter ^e   Chang, Leland ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

^c Von Hoerner and Sulger GmbH Schwetzingen   (Germany)

^d IBM JAPAN LTD   (Japan)

^e IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; ERROR CORRECTION; MEMORY ARCHITECTURE; SEMICONDUCTOR STORAGE;

ERROR-CORRECTION SCHEMES; HARDWARE CHARACTERISTICS; HIGH-EFFICIENCY; HIGH-PERFORMANCE MICROPROCESSORS; LOW-FREQUENCY; MEMORY CELL SIZE; REGISTER FILES; WRITE OPERATIONS;

CYTOLOGY;

EID: 79955710574     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746308     Document Type: Conference Paper

References (3)

1. C. Johnson, et al., "A Wire-Speed Power™ Processor: 2.3GHz 45nm SOI with 16 Cores and 64 Threads," ISSCC Dig. Tech. Papers, pp. 104-105, Feb. 2010.
2. E. S. Fetzer, et al., "A Fully Bypassed Six-Issue Integer Datapath and Register File on the Itanium-2 Microprocessor," IEEE J. Solid-State Circuits, vol. 37, no. 11, Nov. 2002, pp. 1433-1440.
3. D. Wendel, et al., "The Implementation of POWER7™: A Highly Parallel and Scalable Multi-Core High-End Server Processor," ISSCC Dig. Tech. Papers, pp. 102-103, Feb. 2010.