Application of Hardness-By-Design Methodology to radiation-tolerant ASIC Technologies

IEEE Transactions on Nuclear Science

Volumn 47, Issue 6 III, 2000, Pages 2334-2341

  Lacoe, Ronald C ^a,b   Osborn, Jon V ^a,b   Koga, Rocky ^a,b   Brown, Stephanie ^b   Mayer, Donald C ^a,b  

^a IEEE

^b AEROSPACE CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DOSIMETRY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; IRRADIATION; MICROELECTRONIC PROCESSING; MICROELECTRONICS; RADIATION EFFECTS;

HARDNESS-BY-DESIGN METHODOLOGY;

RADIATION HARDENING;

EID: 0034450465     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.903774     Document Type: Conference Paper

References (11)

1. Design issues for radiation tolerant microcircuits in space
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6. Total dose radiation tolerance of a commercial 0.35 μm CMOS process
7. Total dose hardness of a chartered semiconductor 0.35 μm CMOS process
8. Radiation tolerance on the road to 0.25-μm technology
9. Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: Practical design aspects
10. Mitigating single event upsets from combinational logic