Analysis of soft error mitigation techniques for register files in IBM Cu-08 90nm technology

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2006, Pages 515-519

  Naseer, Riaz ^a   Bhatti, Rashed Zafar ^a   Draper, Jeff ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; FAULT TOLERANCE; NANOTECHNOLOGY; REDUNDANCY; WORD PROCESSING;

HAMMING CODES; REGISTER FILES; SINGLE ERROR CORRECTION (SEC); SOFT ERROR MITIGATION TECHNIQUES; TRIPLE MODULAR REDUNDANCY (TMR);

INTEGRATED CIRCUIT LAYOUT;

EID: 34748921576     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2006.382112     Document Type: Conference Paper

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