Logic soft errors in Sub-65nm technologies design and CAD challenges

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 2-4

  Mitra, Subhasish ^a   Karnik, Tanay ^a   Seifert, Norbert ^a   Zhang, Ming ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Architectural Vulnerability Factor; Built In Soft Error Resilience; Derating; Error blocking; Error detection; Recovery; Soft error

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER NETWORKS; COST EFFECTIVENESS; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; PROBLEM SOLVING; RECOVERY;

ARCHITECTURAL VULNERABILITY FACTOR; BUILT-IN SOFT ERROR RESILIENCE; DERATING; ERROR BLOCKING; SOFT ERRORS;

FORMAL LOGIC;

EID: 27944502944     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193762     Document Type: Conference Paper

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