-
2
-
-
0242636503
-
A 1.5-GHz 130-nm Itanium-2 Processor with 6-MB on-die L3 Cache
-
S. Rusu, J. Stinson, S. Tam, J. Leung, H. Muljono, and B. Cherkauer, “A 1.5-GHz 130-nm Itanium-2 Processor with 6-MB on-die L3 Cache,” IEEE J. Solid-State Circuits, vol. 38, no. 11, Nov. 2003, pp.1887–1895.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.11
, pp. 1887-1895
-
-
Rusu, S.1
Stinson, J.2
Tam, S.3
Leung, J.4
Muljono, H.5
Cherkauer, B.6
-
3
-
-
19944426947
-
A 130-nm Triple-Vt 9-MB Third-Level On-Die Cache for the 1.7-GHz Itanium-2 Processor
-
J. Chang, S. Rusu, J. Shoemaker, S. Tam, H. Ming, M. Haque, et al., “A 130-nm Triple-Vt 9-MB Third-Level On-Die Cache for the 1.7-GHz Itanium-2 Processor,” IEEE J. Solid-State Circuits, vol. 40, no. 1, Jan. 2005, pp. 195–203.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.1
, pp. 195-203
-
-
Chang, J.1
Rusu, S.2
Shoemaker, J.3
Tam, S.4
Ming, H.5
Haque, M.6
-
4
-
-
28144457882
-
The Asynchronous 24MB On-Chip Level-3 Cache for a Dual-Core Itanium Family Processor
-
J. Wuu et al., “The Asynchronous 24MB On-Chip Level-3 Cache for a Dual-Core Itanium Family Processor,” Proc. Int. Solid-State Circuits Conf., 2005, pp. 488–489.
-
(2005)
Proc. Int. Solid-State Circuits Conf
, pp. 488-489
-
-
Wuu, J.1
-
5
-
-
61549091687
-
A Dual Core Multi Threaded Xeon Processor with 16MB L3 Cache
-
S. Rusu et al., “A Dual Core Multi Threaded Xeon Processor with 16MB L3 Cache,” IEEE Int. Solid-State Circuits Conf., 2006, pp. 315–324.
-
(2006)
IEEE Int. Solid-State Circuits Conf
, pp. 315-324
-
-
Rusu, S.1
-
6
-
-
0024103902
-
Radiation Effects on Microelectronics in Space
-
J. Srour and J. McGarrity, “Radiation Effects on Microelectronics in Space,” Proc. of the IEEE, vol. 76, no. 11, Nov. 1988, pp. 1443–1469.
-
(1988)
Proc. of the IEEE
, vol.76
, Issue.11
, pp. 1443-1469
-
-
Srour, J.1
McGarrity, J.2
-
7
-
-
0024104046
-
The Space Radiation Environment for Electronics
-
E. Stassinopoulos and J. Raymond, “The Space Radiation Environment for Electronics,” Proc. of the IEEE, vol. 76, no. 11, Nov. 1988, pp. 1423–1442.
-
(1988)
Proc. of the IEEE
, vol.76
, Issue.11
, pp. 1423-1442
-
-
Stassinopoulos, E.1
Raymond, J.2
-
8
-
-
0024104188
-
The Design of Radiation-Hardened ICs for Space: A Compendium of Approaches
-
S. Kerns, B. Shafer, L. Rockett, J. Pridmore, D. Berndt, N. van Vonno, et al., “The Design of Radiation-Hardened ICs for Space: A Compendium of Approaches,” Proc. of the IEEE, vol. 76, no. 11, Nov. 1988, pp. 1470–1509.
-
(1988)
Proc. of the IEEE
, vol.76
, Issue.11
, pp. 1470-1509
-
-
Kerns, S.1
Shafer, B.2
Rockett, L.3
Pridmore, J.4
Berndt, D.5
Van Vonno, N.6
-
9
-
-
0033311541
-
Radiation Tolerant VLSI Circuits in Standard Deep Submicron CMOS Technologies for the LHC Experiments: Practical Design Aspects
-
G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S. Floria, A. Giraldo, et al., “Radiation Tolerant VLSI Circuits in Standard Deep Submicron CMOS Technologies for the LHC Experiments: Practical Design Aspects,” IEEE Trans. Nuc. Sci., vol. 46, no. 6, Dec. 1999, pp. 1690–1696.
-
(1999)
IEEE Trans. Nuc. Sci
, vol.46
, Issue.6
, pp. 1690-1696
-
-
Anelli, G.1
Campbell, M.2
Delmastro, M.3
Faccio, F.4
Floria, S.5
Giraldo, A.6
-
10
-
-
84939046223
-
An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM
-
H. Weaver, C. Axness, J. McBrayer, J. Browning, J. Fu, A. Ochoa, et al., “An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM,” IEEE Trans. Nuc. Sci., vol. 34, no. 6, Dec. 1987, pp. 1281–1286.
-
(1987)
IEEE Trans. Nuc. Sci
, vol.34
, Issue.6
, pp. 1281-1286
-
-
Weaver, H.1
Axness, C.2
McBrayer, J.3
Browning, J.4
Fu, J.5
Ochoa, A.6
-
11
-
-
0033324901
-
BUSFET—A Radiation-Hardened SOI Transistor
-
J. Schwank, M. Shaneyfelt, B. Draper, and P. Dodd, “BUSFET—A Radiation-Hardened SOI Transistor,” IEEE Trans. Nuc. Sci., vol. 46, no. 6, Dec. 1999, pp. 1809–1817.
-
(1999)
IEEE Trans. Nuc. Sci
, vol.46
, Issue.6
, pp. 1809-1817
-
-
Schwank, J.1
Shaneyfelt, M.2
Draper, B.3
Dodd, P.4
-
12
-
-
37249048424
-
The Effect of Active Delay Element Resistance on Limiting Heavy Ion SEU Upset Cross-Sections of SOI ADE/SRAMs
-
S. Liu, D. Nelson, J. Tsang, K. Golke, P. Fechner, W. Heikkila, et al., “The Effect of Active Delay Element Resistance on Limiting Heavy Ion SEU Upset Cross-Sections of SOI ADE/SRAMs,” IEEE Trans. Nuc. Sci., vol. 54, no. 6, Dec. 2007, pp. 2480–2487.
-
(2007)
IEEE Trans. Nuc. Sci
, vol.54
, Issue.6
, pp. 2480-2487
-
-
Liu, S.1
Nelson, D.2
Tsang, J.3
Golke, K.4
Fechner, P.5
Heikkila, W.6
-
13
-
-
0034450465
-
Application of Hardness-by-Design Methodology to Radiation-Tolerant ASIC Technologies
-
R. Lacoe, J. Osborne, R. Koga, and D. Mayer, “Application of Hardness-by-Design Methodology to Radiation-Tolerant ASIC Technologies,” IEEE Trans. Nuc. Sci., vol. 47, no. 6, Dec. 2000, pp. 2334–2341.
-
(2000)
IEEE Trans. Nuc. Sci
, vol.47
, Issue.6
, pp. 2334-2341
-
-
Lacoe, R.1
Osborne, J.2
Koga, R.3
Mayer, D.4
-
14
-
-
0038107834
-
Total Ionizing Dose Effects in MOS Oxides and Devices
-
T. Oldham and F. McLean, “Total Ionizing Dose Effects in MOS Oxides and Devices,” IEEE Trans. Nuc. Sci., vol. 50, no. 3, June 2003, pp. 483–499.
-
(2003)
IEEE Trans. Nuc. Sci
, vol.50
, Issue.3
, pp. 483-499
-
-
Oldham, T.1
McLean, F.2
-
15
-
-
33846289564
-
Total-Ionizing-Dose Effects in Modern CMOS Technologies
-
H. Barnaby, “Total-Ionizing-Dose Effects in Modern CMOS Technologies,” IEEE Trans. Nuc. Sci., vol. 53, no. 6, Dec. 2006, pp. 3103–3121.
-
(2006)
IEEE Trans. Nuc. Sci
, vol.53
, Issue.6
, pp. 3103-3121
-
-
Barnaby, H.1
-
16
-
-
33846304220
-
Radiation Response and Variability of Advanced Commercial Foundry Technologies
-
J. Felix, P. Dodd, M. Shaneyfelt, J. Schwank, and G. Hash, “Radiation Response and Variability of Advanced Commercial Foundry Technologies,” IEEE Trans. Nuc. Sci., vol. 53, no. 6, Dec. 2006, pp. 3187–3194.
-
(2006)
IEEE Trans. Nuc. Sci
, vol.53
, Issue.6
, pp. 3187-3194
-
-
Felix, J.1
Dodd, P.2
Shaneyfelt, M.3
Schwank, J.4
Hash, G.5
-
17
-
-
58849108228
-
The Impact of Total Ionizing Dose on Unhardened SRAM Cell Margins
-
X. Yao, N. Hindman, L. Clark, K. Holbert, D. Alexander, and W. Shedd, “The Impact of Total Ionizing Dose on Unhardened SRAM Cell Margins,” IEEE Trans. Nuc. Sci., vol. 55, no. 6, Dec. 2008, pp. 3280–3287.
-
(2008)
IEEE Trans. Nuc. Sci
, vol.55
, Issue.6
, pp. 3280-3287
-
-
Yao, X.1
Hindman, N.2
Clark, L.3
Holbert, K.4
Alexander, D.5
Shedd, W.6
-
18
-
-
0030375853
-
Upset Hardened Memory Design for Submicron CMOS Technology
-
T. Calin, M. Nicolaidis, and R. Velazco, “Upset Hardened Memory Design for Submicron CMOS Technology,” IEEE Trans. Nuc. Sci., vol. 43, no. 6, Dec. 1996, pp. 2874–2878.
-
(1996)
IEEE Trans. Nuc. Sci
, vol.43
, Issue.6
, pp. 2874-2878
-
-
Calin, T.1
Nicolaidis, M.2
Velazco, R.3
-
19
-
-
33144457082
-
-
Proc. RADECS
-
R. Koga, K. Crawford, P. Grant, W. Kolasinski, D. Leung, T. Lie, et al., “Single Ion Induced Multiple-Bit Upset in IDT 256K SRAMs,” Proc. RADECS, Sept. 1993, pp. 485–489.
-
(1993)
Single Ion Induced Multiple-Bit Upset in IDT 256K Srams
, pp. 485-489
-
-
Koga, R.1
Crawford, K.2
Grant, P.3
Kolasinski, W.4
Leung, D.5
Lie, T.6
-
20
-
-
84939707512
-
Observations of Single-event Upset And Multiple-Bit Upset in Non-hardened High-Density SRAMs in the TOPEX/Poseidon Orbit
-
C. Underwood, R. Ecoffet, S. Duzeffier, and D. Faguere, “Observations of Single-event Upset And Multiple-Bit Upset in Non-hardened High-Density SRAMs in the TOPEX/Poseidon Orbit,” IEEE Rad. Effects Data Workshop, July 1993, pp. 85–92.
-
(1993)
IEEE Rad. Effects Data Workshop
, pp. 85-92
-
-
Underwood, C.1
Ecoffet, R.2
Duzeffier, S.3
Faguere, D.4
-
21
-
-
0036082034
-
Soft Error Rate Mitigation Techniques for Modern Microcircuits
-
D. Mavis and P. Eaton, “Soft Error Rate Mitigation Techniques for Modern Microcircuits,” Proc. IRPS, 2002, pp. 216–225.
-
(2002)
Proc. IRPS
, pp. 216-225
-
-
Mavis, D.1
Eaton, P.2
-
22
-
-
84939046223
-
An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM
-
H. Weaver, C. Axness, J. McBrayer, J. Browning, A. Fu, A. Ochoa, et al., “An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM,” IEEE Trans. Nuc. Sci., vol. 34, no. 6, Dec. 1987, pp. 1281–1286.
-
(1987)
IEEE Trans. Nuc. Sci
, vol.34
, Issue.6
, pp. 1281-1286
-
-
Weaver, H.1
Axness, C.2
McBrayer, J.3
Browning, J.4
Fu, A.5
Ochoa, A.6
-
23
-
-
84939044292
-
Characterization of an Ultra-Hard CMOS 64K Static RAM
-
W. Jenkins, R. Martin, and H. Hughes, “Characterization of an Ultra-Hard CMOS 64K Static RAM,” IEEE Trans. Nuc. Sci., vol. 34, no. 6, part I, Dec. 1987, pp. 1455–1459.
-
(1987)
IEEE Trans. Nuc. Sci
, vol.34
, Issue.6
, pp. 1455-1459
-
-
Jenkins, W.1
Martin, R.2
Hughes, H.3
-
24
-
-
34547273523
-
Radiation Hardened 128K PDSOI CMOS Static RAM
-
Z. Kai, L. Zhongli, Y. Fang, X. Zhiqiang, and H. Genshen, “Radiation Hardened 128K PDSOI CMOS Static RAM,” Proc. ICSICT, 2006, pp. 1922–1924.
-
(2006)
Proc. ICSICT
, pp. 1922-1924
-
-
Kai, Z.1
Zhongli, L.2
Fang, Y.3
Zhiqiang, X.4
Genshen, H.5
-
25
-
-
0024942287
-
Non-random Single Event Upset Trends
-
P. McDonald, W. Stapor, A. Campbell, and L. Massengill, “Non-random Single Event Upset Trends,” IEEE Trans. Nuc. Sci, vol. 36, no. 6, Dec. 1989, pp. 2324–2329.
-
(1989)
IEEE Trans. Nuc. Sci
, vol.36
, Issue.6
, pp. 2324-2329
-
-
McDonald, P.1
Stapor, W.2
Campbell, A.3
Massengill, L.4
-
26
-
-
0028705540
-
SEU Immunity: The Effects of Scaling on the Peripheral Circuits of SRAMs
-
L Jacunski et al., “SEU Immunity: The Effects of Scaling on the Peripheral Circuits of SRAMs,” IEEE Trans. Nuc. Sci, vol. 41, no. 6, Dec. 1994, 2272–2276.
-
(1994)
IEEE Trans. Nuc. Sci
, vol.41
, Issue.6
, pp. 2272-2276
-
-
Jacunski, L.1
-
27
-
-
0842266592
-
Characterization of Multi-bit Soft Error Events in Advanced SRAMs
-
J. Maiz, S. Hareland, K. Zhang, and P. Armstrong, “Characterization of Multi-bit Soft Error Events in Advanced SRAMs,” IEDM Tech. Dig., Dec. 2003, pp. 21.4.1–21.4.4.
-
(2003)
IEDM Tech. Dig
, pp. 1-21
-
-
Maiz, J.1
Hareland, S.2
Zhang, K.3
Armstrong, P.4
-
28
-
-
58849108988
-
Multiple Bit Upsets and Error Mitigation in Ultra-Deep Submicron SRAMs
-
D. Mavis et al., “Multiple Bit Upsets and Error Mitigation in Ultra-Deep Submicron SRAMs,” IEEE Trans. Nuc. Sci., vol. 55, no. 6, Dec. 2008, pp. 3288–3294.
-
(2008)
IEEE Trans. Nuc. Sci
, vol.55
, Issue.6
, pp. 3288-3294
-
-
Mavis, D.1
-
30
-
-
33846287541
-
An Area and Power Efficient Radiation Hardened by Design Flip-Flop
-
J. Knudsen and L. Clark, “An Area and Power Efficient Radiation Hardened by Design Flip-Flop,” IEEE Trans. Nuc. Sci., vol. 53, no. 6, Dec. 2006, pp. 3392–3399.
-
(2006)
IEEE Trans. Nuc. Sci
, vol.53
, Issue.6
, pp. 3392-3399
-
-
Knudsen, J.1
Clark, L.2
-
31
-
-
0030285348
-
A 160MHz, 32b 0.5W CMOS RISC Microprocessor
-
J. Montonarro et al., “A 160MHz, 32b 0.5W CMOS RISC Microprocessor,” IEEE J. of Solid-state Circ., vol. 31, no. 11, Nov. 1996, pp. 1703–1714.
-
(1996)
IEEE J. of Solid-State Circ
, vol.31
, Issue.11
, pp. 1703-1714
-
-
Montonarro, J.1
-
32
-
-
0035507074
-
An Embedded Microprocessor Core for High Performance and Low Power Applications
-
L. Clark, E. Hoffman, J. Miller, M. Biyani, Y. Liao, S. Strazdus, et al., “An Embedded Microprocessor Core for High Performance and Low Power Applications,” IEEE J. of Solid-State Circ., vol. 36, no. 11, Nov. 2001, pp. 1599–1608.
-
(2001)
IEEE J. of Solid-State Circ
, vol.36
, Issue.11
, pp. 1599-1608
-
-
Clark, L.1
Hoffman, E.2
Miller, J.3
Biyani, M.4
Liao, Y.5
Strazdus, S.6
-
33
-
-
34548713486
-
-
Proc. IRPS
-
L. Clark, K. Mohr, and K. Holbert, “Reverse-Body Biasing for Radiation-Hard by Design Logic Gates,” Proc. IRPS, April 2007, pp. 582–583.
-
(2007)
Reverse-Body Biasing for Radiation-Hard by Design Logic Gates
, pp. 582-583
-
-
Clark, L.1
Mohr, K.2
Holbert, K.3
-
34
-
-
0035308547
-
The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability
-
A. Bhavnagarwala, T. Xinghai, and J. Meindl, “The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability,” IEEE J. Solid-State Circ., vol. 36, no. 4, Apr. 2001, pp. 658–665.
-
(2001)
IEEE J. Solid-State Circ
, vol.36
, Issue.4
, pp. 658-665
-
-
Bhavnagarwala, A.1
Xinghai, T.2
Meindl, J.3
-
35
-
-
84886738383
-
-
Proc. ISQED
-
E. Grossar, M. Stucchi, K. Maex, and W. Dehaene, “Statistically Aware SRAM Memory Array Design,” Proc. ISQED, March 2006.
-
(2006)
Statistically Aware SRAM Memory Array Design
-
-
Grossar, E.1
Stucchi, M.2
Maex, K.3
Dehaene, W.4
-
36
-
-
16244371339
-
Variability in Sub-100nm SRAM Designs
-
R. Heald and P. Wang, “Variability in Sub-100nm SRAM Designs,” Proc. ICCAD-2004, Nov. 2004, pp. 347–352.
-
(2004)
Proc. ICCAD-2004
, pp. 347-352
-
-
Heald, R.1
Wang, P.2
-
37
-
-
34548834449
-
A New Combined Methodology for Write-Margin Extraction of Advanced SRAM
-
N. Gierczynski, B. Borot, N. Planes, and H. Brut, “A New Combined Methodology for Write-Margin Extraction of Advanced SRAM,” IEEE Int. Conf. on Microelectronic Test Structures, March 2007, pp. 97–100.
-
(2007)
IEEE Int. Conf. on Microelectronic Test Structures
, pp. 97-100
-
-
Gierczynski, N.1
Borot, B.2
Planes, N.3
Brut, H.4
-
38
-
-
0023437909
-
Static-Noise Margin Analysis of MOS SRAM Cells
-
E. Seevinck, F. List, and J. Lohstroh, “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE J. Solid-State Circ., vol. SC-22, no. 5, Oct. 1987, pp. 748–754.
-
(1987)
IEEE J. Solid-State Circ
, vol.22
, Issue.5
, pp. 748-754
-
-
Seevinck, E.1
List, F.2
Lohstroh, J.3
-
40
-
-
0036949550
-
-
Proc. ISLPED
-
L. Clark, N. Deutscher, F. Ricci, and S. Demmons, “Standby Power Management for a 0.18 μm Microprocessor,” Proc. ISLPED, Aug. 2002, pp. 7–12.
-
(2002)
Standby Power Management for a 0.18 μm Microprocessor
, pp. 7-12
-
-
Clark, L.1
Deutscher, N.2
Ricci, F.3
Demmons, S.4
-
41
-
-
0030121481
-
Driving Source-Line Cell Architecture for Sub-1V High-Speed Low-Power Applications
-
H. Mizuno and T. Nagano, “Driving Source-Line Cell Architecture for Sub-1V High-Speed Low-Power Applications,” IEEE J. Solid-State Circ., vol. 31, no. 4, Apr. 1996, pp. 552–557.
-
(1996)
IEEE J. Solid-State Circ
, vol.31
, Issue.4
, pp. 552-557
-
-
Mizuno, H.1
Nagano, T.2
-
42
-
-
0033221245
-
An 18-μA Standby Current 1.8-V, 200-MHz Microprocessor with Self-Substrate-Biased Data-Retention Mode
-
H. Mizuno et al., “An 18-μA Standby Current 1.8-V, 200-MHz Microprocessor with Self-Substrate-Biased Data-Retention Mode,” IEEE J. Solid-State Circ., vol. 34, no. 11, Nov. 1999, pp. 1492–1500.
-
(1999)
IEEE J. Solid-State Circ
, vol.34
, Issue.11
, pp. 1492-1500
-
-
Mizuno, H.1
-
43
-
-
1642310480
-
Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power
-
N. Kim, K. Flautner, D. Blaauw, and T. Mudge, “Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power,” IEEE Trans. VLSI Sys., vol. 12, no. 2, Feb. 2004, pp. 167–184.
-
(2004)
IEEE Trans. VLSI Sys
, vol.12
, Issue.2
, pp. 167-184
-
-
Kim, N.1
Flautner, K.2
Blaauw, D.3
Mudge, T.4
-
44
-
-
85057420252
-
-
PXA27x Processor Family Power Requirements Application Note
-
PXA27x Processor Family Power Requirements Application Note. Available at: http://www.marvel.com
-
-
-
-
45
-
-
4544284413
-
Transistor Optimization for Leakage Power Management in a 65 nm CMOS Technology for Wireless and Mobile Applications
-
S. Zhao et al., “Transistor Optimization for Leakage Power Management in a 65 nm CMOS Technology for Wireless and Mobile Applications,” IEEE Symp. VLSI Tech. Dig. Tech. Papers, June 2004, pp. 14–15.
-
(2004)
IEEE Symp. VLSI Tech. Dig. Tech. Papers
, pp. 14-15
-
-
Zhao, S.1
-
46
-
-
0033342041
-
Enhanced Total Ionizing Dose Tolerance of Bulk CMOS Transistors Fabricated for Ultra-Low Power Applications
-
M. Xapsos, G. Summers, and E. Jackson, “Enhanced Total Ionizing Dose Tolerance of Bulk CMOS Transistors Fabricated for Ultra-Low Power Applications,” IEEE Trans. Nuc. Sci., vol. 46, no. 6, Dec. 1999, pp. 1697–1701.
-
(1999)
IEEE Trans. Nuc. Sci
, vol.46
, Issue.6
, pp. 1697-1701
-
-
Xapsos, M.1
Summers, G.2
Jackson, E.3
-
47
-
-
37249043765
-
Optimizing Radiation Hard by Design SRAM Cells
-
L. Clark, K. Mohr, K. Holbert, X. Yao, J. Knudsen, and H. Shah, “Optimizing Radiation Hard by Design SRAM Cells,” IEEE Trans. Nuc. Sci., vol. 54, no. 6, Dec. 2007, pp. 2028–2036.
-
(2007)
IEEE Trans. Nuc. Sci
, vol.54
, Issue.6
, pp. 2028-2036
-
-
Clark, L.1
Mohr, K.2
Holbert, K.3
Yao, X.4
Knudsen, J.5
Shah, H.6
-
48
-
-
37249087436
-
A 130-nm RHBD SRAM with High Speed SET and Area Efficient TID Mitigation
-
K. Mohr, L. Clark, and K. Holbert, “A 130-nm RHBD SRAM with High Speed SET and Area Efficient TID Mitigation,” IEEE Trans. Nucl. Sci., vol. 54, no. 6, December 2007, pp. 2092–2099.
-
(2007)
IEEE Trans. Nucl. Sci
, vol.54
, Issue.6
, pp. 2092-2099
-
-
Mohr, K.1
Clark, L.2
Holbert, K.3
-
49
-
-
33646072123
-
Hybrid-Orientation Technology (HOT): Opportunities and Challenges
-
C. Yang, K. Chan, L. Shi, D. Fried, J. Stathis, A. Chou, et al., “Hybrid-Orientation Technology (HOT): Opportunities and Challenges,” IEEE Trans. Electron Dev., vol. 53, no. 5, May 2006, pp. 965–978.
-
(2006)
IEEE Trans. Electron Dev
, vol.53
, Issue.5
, pp. 965-978
-
-
Yang, C.1
Chan, K.2
Shi, L.3
Fried, D.4
Stathis, J.5
Chou, A.6
-
50
-
-
57849140228
-
Modeling Ionizing Radiation Effects in Solid State Materials and CMOS Devices
-
H. Barnaby, M. Mclain, I. Esqueda, and X. Chen, “Modeling Ionizing Radiation Effects in Solid State Materials and CMOS Devices,” Proc. IEEE CICC, Sept. 2008 pp. 273–280.
-
(2008)
Proc. IEEE CICC
, pp. 273-280
-
-
Barnaby, H.1
McLain, M.2
Esqueda, I.3
Chen, X.4
-
51
-
-
0037321205
-
A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron
-
A. Agarwal, L. Hai, and K. Roy, “A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron,” IEEE J. Solid-State Circ., vol. 38, no. 2, Feb. 2003, pp. 319–328.
-
(2003)
IEEE J. Solid-State Circ
, vol.38
, Issue.2
, pp. 319-328
-
-
Agarwal, A.1
Hai, L.2
Roy, K.3
-
52
-
-
0003699181
-
-
Lattice Press, Long Beach, CA
-
S. Wolf, Silicon Processing for the VLSI Era, Volume 3—The Submicron MOSFET, Lattice Press, Long Beach, CA, 1995.
-
(1995)
Silicon Processing for the VLSI Era, Volume 3—The Submicron MOSFET
-
-
Wolf, S.1
-
53
-
-
33749402575
-
The Impact of Substrate Bias on Proton Damage in 130 nm CMOS Technology
-
B. Haugerud et al., “The Impact of Substrate Bias on Proton Damage in 130 nm CMOS Technology,” Radiation Effects Data Workshop Record, July 2005, pp. 117–121.
-
(2005)
Radiation Effects Data Workshop Record
, pp. 117-121
-
-
Haugerud, B.1
-
54
-
-
58849091394
-
Characterizing SRAM Single Event Upset in Terms of Single and Multiple Node Charge Collection
-
J. Black et al., “Characterizing SRAM Single Event Upset in Terms of Single and Multiple Node Charge Collection,” IEEE Trans. Nuc. Sci., vol. 55, no. 6, Dec. 2008, pp. 2943–2947.
-
(2008)
IEEE Trans. Nuc. Sci
, vol.55
, Issue.6
, pp. 2943-2947
-
-
Black, J.1
-
56
-
-
65849528344
-
Gridded Design Rule Scaling: Taking the CPU towards the 16 nm Node
-
C. Bencher, H. Dai, and Y. Chen, “Gridded Design Rule Scaling: Taking the CPU towards the 16 nm Node,” Proc. SPIE, vol. 7274, 2009, pp. 0G-1–0G-10.
-
(2009)
Proc. SPIE
, vol.7274
, pp. 0G-1G
-
-
Bencher, C.1
Dai, H.2
Chen, Y.3
|