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Volumn 51, Issue 6 II, 2004, Pages 3285-3290

Single event transient pulsewidths in digital microcircuits

Author keywords

Digital single event transients (DSETs); Heavy ions; Single event effects (SEEs); SPICE

Indexed keywords

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; ERROR ANALYSIS; HEAVY IONS; IONIZATION; RADIATION EFFECTS;

EID: 11044230874     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.839174     Document Type: Conference Paper
Times cited : (127)

References (14)
  • 1
    • 0031367158 scopus 로고    scopus 로고
    • Comparison of error rates in combinatorial and sequential logic
    • Dec.
    • S. Buchner, M. Baze, D. Brown, D. McMorrow, and J. Melinger, "Comparison of error rates in combinatorial and sequential logic," IEEE Trans. Nucl. Sci., vol. 44, pp. 2209-2216, Dec. 1997.
    • (1997) IEEE Trans. Nucl. Sci. , vol.44 , pp. 2209-2216
    • Buchner, S.1    Baze, M.2    Brown, D.3    McMorrow, D.4    Melinger, J.5
  • 5
    • 0034452351 scopus 로고    scopus 로고
    • Analysis of single-event effects in combinational logic - Simulation of the AM2901 bitslice processor
    • Dec.
    • L. W. Massengill, A. E. Baranski, D. O. Van Nort, J. Meng, and B. L. Bhuva, "Analysis of single-event effects in combinational logic - simulation of the AM2901 bitslice processor," IEEE Trans. Nucl. Sci., vol. 47, pp. 2609-2615, Dec. 2000.
    • (2000) IEEE Trans. Nucl. Sci. , vol.47 , pp. 2609-2615
    • Massengill, L.W.1    Baranski, A.E.2    Van Nort, D.O.3    Meng, J.4    Bhuva, B.L.5
  • 8
    • 0031373956 scopus 로고    scopus 로고
    • Attenuation of single event induced pulses in CMOS combinatorial logic
    • Dec.
    • M. P. Baze and S. P. Buchner, "Attenuation of single event induced pulses in CMOS combinatorial logic," IEEE Trans. Nucl. Sci., vol. 44, pp. 2217-2223, Dec. 1997.
    • (1997) IEEE Trans. Nucl. Sci. , vol.44 , pp. 2217-2223
    • Baze, M.P.1    Buchner, S.P.2
  • 10
    • 0030375853 scopus 로고    scopus 로고
    • Upset hardened memory design for submicron CMOS technology
    • Dec.
    • T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, pp. 2874-2878, Dec. 1996.
    • (1996) IEEE Trans. Nucl. Sci. , vol.43 , pp. 2874-2878
    • Calin, T.1    Nicolaidis, M.2    Velazco, R.3
  • 13
    • 0038721289 scopus 로고    scopus 로고
    • Basic mechanisms and modeling of single-event upset in digital microelectronics
    • June
    • P. E. Dodd and L. W. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics," IEEE Trans. Nucl. Sci., vol. 50, pp. 583-602, June 2003.
    • (2003) IEEE Trans. Nucl. Sci. , vol.50 , pp. 583-602
    • Dodd, P.E.1    Massengill, L.W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.