Radiation tolérant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: Practical design aspects

IEEE Transactions on Nuclear Science

Volumn 46, Issue 6 PART 1, 1999, Pages 1690-1696

  Anelli, G ^a   Campbell, M ^a   Delmastro, M ^a   Faccio, F ^a   Florian, S ^a   Giraldo, A ^a   Heijne, E ^a   Jarron, P ^a   Kloukinas, K ^b   Marchioro, A ^b   Moreira, P ^b   Snoeys, W ^b  

^a CERN   (Switzerland)

^b UNIVERSITY OF PADOVA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); NEUTRON IRRADIATION; PROTON IRRADIATION; SIGNAL NOISE MEASUREMENT; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

DEEP SUBMICRON TECHNOLOGIES; ENCLOSED LAYOUT TRANSISTORS; FIELD OXIDE TRANSISTORS; LARGE HADRON COLLIDER; RADIATION TOLERANCE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033311541     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.819140     Document Type: Article

References (16)

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