-
1
-
-
11044239423
-
Production and propagation of single-event transients in high-speed digital logic ICs
-
DOI 10.1109/TNS.2004.839172
-
P. Dodd, M. R. Shaneyfelt, J. A. Felix, and J. R. Schwank, "Production and propagation of single-event transients in high-speed digital logic ICs," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3278-3284, Dec. 2004. (Pubitemid 40044005)
-
(2004)
IEEE Transactions on Nuclear Science
, vol.51
, Issue.2
, pp. 3278-3284
-
-
Dodd, P.E.1
Shaneyfelt, M.R.2
Felix, J.A.3
Schwank, J.R.4
-
2
-
-
11044230874
-
Single event transient pulsewidths in digital microcircuits
-
DOI 10.1109/TNS.2004.839174
-
M. Gadlage, R. D. Schrimpf, J. M. Benedetto, P. H. Eaton, D. G. Mavis, M. Sibley, K. Avery, and T. L. Turflinger, "Single event transient pulse widths in digital microcircuits," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3285-3290, Dec. 2004. (Pubitemid 40044006)
-
(2004)
IEEE Transactions on Nuclear Science
, vol.51
, Issue.2
, pp. 3285-3290
-
-
Gadlage, M.J.1
Schrimpf, R.D.2
Benedetto, J.M.3
Eaton, P.H.4
Mavis, D.G.5
Sibley, M.6
Avery, K.7
Turflinger, T.L.8
-
3
-
-
33846300633
-
Digital single event transient trends with technology node scaling
-
DOI 10.1109/TNS.2006.886044
-
J. M. Benedetto, P. H. Eaton, D. G. Mavis, M. Gadlage, and T. Turflinger, "Digital single event transient trends with technology node scaling," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3462-3465, Dec. 2006. (Pubitemid 46113349)
-
(2006)
IEEE Transactions on Nuclear Science
, vol.53
, Issue.6
, pp. 3462-3465
-
-
Benedetto, J.M.1
Eaton, P.H.2
Mavis, D.G.3
Gadlage, M.4
Turflinger, T.5
-
4
-
-
0029536513
-
Critical charge concepts for CMOS SRAMs
-
Dec
-
P. Dodd and F. Sexton, "Critical charge concepts for CMOS SRAMs," IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1764-1771, Dec. 1995.
-
(1995)
IEEE Trans. Nucl. Sci.
, vol.42
, Issue.6
, pp. 1764-1771
-
-
Dodd, P.1
Sexton, F.2
-
5
-
-
34548726215
-
A radiation hardened 16-Mb SRAM for space applica-tions
-
T. Hoang, J. Ross, S. Doyle, D. Rea, E. Chan, W. Neiderer, and A. Bumgarner, "A radiation hardened 16-Mb SRAM for space applica-tions," in Proc. IEEE Aerospace Conf., 2007, pp. 1-6.
-
(2007)
Proc. IEEE Aerospace Conf
, pp. 1-6
-
-
Hoang, T.1
Ross, J.2
Doyle, S.3
Rea, D.4
Chan, E.5
Neiderer, W.6
Bumgarner, A.7
-
6
-
-
0033311541
-
Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects
-
G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S. Floria, A. Gi-raldo, E. Heijne, P. Jarron, K. Kloukinas, A. Marchioro, P. Moreira, and W. Snoeys, "Radiation tolerant VLSI circuits in standard deep sub-micron CMOS technologies for the LHC experiments: practical design aspects," IEEE Trans. Nucl. Sci., vol. 46, no. 6, pp. 1690-1696, Dec. 1999. (Pubitemid 30574193)
-
(1999)
IEEE Transactions on Nuclear Science
, vol.46
, Issue.1
, pp. 1690-1696
-
-
Anelli, G.1
Campbell, M.2
Delmastro, M.3
Faccio, F.4
Florian, S.5
Giraldo, A.6
Heijne, E.7
Jarron, P.8
Kloukinas, K.9
Marchioro, A.10
Moreira, P.11
Snoeys, W.12
-
7
-
-
0034450465
-
Application of Hardness-By-Design Methodology to radiation-tolerant ASIC Technologies
-
DOI 10.1109/23.903774, PII S001894990012687
-
R. Lacoe, J. V. Osborn, R. Koga, S. Brown, and D. C. Mayer, "Appli-cation of hardness-by-design methodology to radiation-tolerant ASIC technologies," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2334-2341, Dec. 2000. (Pubitemid 32325489)
-
(2000)
IEEE Transactions on Nuclear Science
, vol.47
, Issue.2
, pp. 2334-2341
-
-
Lacoe, R.C.1
Osborn, J.V.2
Koga, R.3
Brown, S.4
Mayer, D.C.5
-
8
-
-
72349089021
-
Heavy ion testing and single event upset rate prediction considerations for a DICE flip-flop
-
Dec
-
K. Warren, A. L. Sternberg, J. D. Black, R. A. Weller, R. A. Reed, M. H. Mendenhall, R. D. Schrimpf, and L. W. Massengill, "Heavy ion testing and single event upset rate prediction considerations for a DICE flip-flop," IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3130-3137, Dec. 2009.
-
(2009)
IEEE Trans. Nucl. Sci.
, vol.56
, Issue.6
, pp. 3130-3137
-
-
Warren, K.1
Sternberg, A.L.2
Black, J.D.3
Weller, R.A.4
Reed, R.A.5
Mendenhall, M.H.6
Schrimpf, R.D.7
Massengill, L.W.8
-
9
-
-
72349090776
-
Clock, flip-flop, and combinatorial logic contribu-tions to the SEU cross section in 90 nm ASIC technology
-
Dec
-
D. Hansen etal., "Clock, flip-flop, and combinatorial logic contribu-tions to the SEU cross section in 90 nm ASIC technology," IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3542-3550, Dec. 2009.
-
(2009)
IEEE Trans. Nucl. Sci.
, vol.56
, Issue.6
, pp. 3542-3550
-
-
Hansen, D.1
-
10
-
-
58849147938
-
Extended SET pulses in sequential circuits leading to in-creased SE vulnerability
-
Dec
-
B. Narasimham, O. A. Amusan, B. L. Bhuva, R. D. Schrimpf, and W. T. Holman, "Extended SET pulses in sequential circuits leading to in-creased SE vulnerability," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 3077-3081, Dec. 2008.
-
(2008)
IEEE Trans. Nucl. Sci.
, vol.55
, Issue.6
, pp. 3077-3081
-
-
Narasimham, B.1
Amusan, O.A.2
Bhuva, B.L.3
Schrimpf, R.D.4
Holman, W.T.5
-
11
-
-
80052747346
-
High speed redundant self-correcting circuits for radiation hardened by design logic
-
N. D. Hindman, D. E. Pettit, D. W. Patterson, K. E. Nielsen, X. Yao, K. E. Holbert, and L. T. Clark, "High speed redundant self-correcting circuits for radiation hardened by design logic," Proc. RADECS Conf., pp. 465-472, 2009.
-
(2009)
Proc. RADECS Conf.
, pp. 465-472
-
-
Hindman, N.D.1
Pettit, D.E.2
Patterson, D.W.3
Nielsen, K.E.4
Yao, X.5
Holbert, K.E.6
Clark, L.T.7
-
12
-
-
47849128645
-
Flight SEU performance of the single board computer (SBC) utilizing hardware voted commercial Power PC processors on-board the CALIPSO satellite
-
B. Peters, A. Wardrop, D. Lahti, H. Herzog, T. O'Connor, and R. De- Coursey, "Flight SEU performance of the single board computer (SBC) utilizing hardware voted commercial Power PC processors on-board the CALIPSO satellite," in Proc. IEEE Radiation Effects Workshop, 2007, pp. 16-25.
-
(2007)
Proc. IEEE Radiation Effects Workshop
, pp. 16-25
-
-
Peters, B.1
Wardrop, A.2
Lahti, D.3
Herzog, H.4
O'Connor, T.5
De- Coursey, R.6
-
13
-
-
58849095005
-
Self-voting dual-modular-redundancy circuits for single event transient mitigation
-
Dec
-
J. Teifel, "Self-voting dual-modular-redundancy circuits for single event transient mitigation," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 3435-3439, Dec. 2008.
-
(2008)
IEEE Trans. Nucl. Sci.
, vol.55
, Issue.6
, pp. 3435-3439
-
-
Teifel, J.1
-
14
-
-
0031069405
-
A 600 MHz superscalar RISC microprocessor with out-of-order execution
-
B. Gieseke et al., "A 600 MHz superscalar RISC microprocessor with out-of-order execution," in Proc. IEEE Int. Solid-State Circuits Conf. Tech. Dig., 1997, pp. 176-177.
-
(1997)
Proc. IEEE Int. Solid-State Circuits Conf. Tech. Dig
, pp. 176-177
-
-
Gieseke, B.1
-
15
-
-
31344452990
-
The parity protected, multithreaded register files on the 90-nm itanium microprocessor
-
DOI 10.1109/JSSC.2005.859884
-
E. Fetzer, D. Dahle, C. Little, and K. Safford, "The parity protected, multithreaded register files on the 90-nm itanium microprocessor," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 246-255, Jan. 2006. (Pubitemid 43145982)
-
(2006)
IEEE Journal of Solid-State Circuits
, vol.41
, Issue.1
, pp. 246-255
-
-
Fetzer, E.S.1
Dahle, D.2
Little, C.3
Safford, K.4
-
16
-
-
0014823837
-
A class of optimal minimum odd-weight-column SEC-DEC codes
-
Jul
-
M. Hsiao, "A class of optimal minimum odd-weight-column SEC-DEC codes," IBM J. Res. Develop., vol. 14, no. 4, pp. 395-401, Jul. 1970.
-
(1970)
IBM J. Res. Develop.
, vol.14
, Issue.4
, pp. 395-401
-
-
Hsiao, M.1
-
17
-
-
34548057465
-
A radiation hardened by design register file with lightweight error detection and correction
-
DOI 10.1109/TNS.2007.903173
-
K. Mohr, G. Samson, and L. T. Clark, "A radiation hardened by design register file with low latency and area cost error detection and correc- tion,"IEEE Trans. Nucl. Sci., vol. 54, no. 4, pp. 1335-1342, Aug. 2007. (Pubitemid 47295110)
-
(2007)
IEEE Transactions on Nuclear Science
, vol.54
, Issue.4
, pp. 1335-1342
-
-
Mohr, K.C.1
Samson, G.2
Clark, L.T.3
-
18
-
-
34748921576
-
Analysis of soft error mitigation techniques for register files in IBM Cu-08 90nm technology
-
DOI 10.1109/MWSCAS.2006.382112, 4267189, Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
-
R. Naseer, R. Bhatt, and J. Draper, "Analysis of soft error mitigation techniques for register files in IBM Cu-08 90nm technology," in Proc. IEEE Int. Midwest Symp. Circuitsand Systems, 2006, pp. 515-519. (Pubitemid 47486889)
-
(2006)
Midwest Symposium on Circuits and Systems
, vol.1
, pp. 515-519
-
-
Naseer, R.1
Bhatti, R.Z.2
Draper, J.3
-
19
-
-
84965177762
-
Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy
-
R. Hentschke, F. Marques, F. Lima, L. Carro, A. Susin, and R. Reis, "Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy," in Proc. Symp. Int. Circuitsand Systems Design, 2002, pp. 95-100.
-
(2002)
Proc. Symp. Int. Circuitsand Systems Design
, pp. 95-100
-
-
Hentschke, R.1
Marques, F.2
Lima, F.3
Carro, L.4
Susin, A.5
Reis, R.6
-
20
-
-
0033745487
-
Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout
-
Jun
-
A. Giraldo, A. Paccagnella, and A. Minzoni, "Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout," Solid State Electron., vol. 44, pp. 981-989, Jun. 2000.
-
(2000)
Solid State Electron
, vol.44
, pp. 981-989
-
-
Giraldo, A.1
Paccagnella, A.2
Minzoni, A.3
-
21
-
-
77955826791
-
A 90 nm bulk CMOS radiation hardened by design cache memory
-
Aug
-
X. Yao, D. Patterson, K. Holbert, and L. Clark, "A 90 nm bulk CMOS radiation hardened by design cache memory," IEEE Trans. Nucl. Sci., vol. 57, no. 4, pp. 2089-2097, Aug. 2010.
-
(2010)
IEEE Trans. Nucl. Sci.
, vol.57
, Issue.4
, pp. 2089-2097
-
-
Yao, X.1
Patterson, D.2
Holbert, K.3
Clark, L.4
|