DF-DICE: A scalable solution for soft error tolerant circuit design

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 3890-3893

  Naseer, Riaz ^a   Draper, Jeff ^b  

^a University of Southern California ^*  (United States)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ERROR ANALYSIS; FLIP FLOP CIRCUITS; LOGIC DESIGN; THRESHOLD LOGIC;

DELAY FILTERED DUAL INTERLOCKED STORAGE CELL (DF-DICE); SOFT ERROR MITIGATION; SOFT ERROR TOLERANT DESIGN;

DELAY CIRCUITS;

EID: 34547326764     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

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