NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2015-January, Issue January, 2015, Pages 458-470

  Jerger, Natalie Enright ^a   Kannan, Ajaykumar ^a   Li, Zimo ^a   Loh, Gabriel H ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; INTEGRATED CIRCUIT INTERCONNECTS; MEMORY ARCHITECTURE; NETWORK ARCHITECTURE; SILICON; THREE DIMENSIONAL INTEGRATED CIRCUITS;

EXPERIMENTAL EVALUATION; MEMORY CAPACITY; MULTICORE CHIPS; NETWORK ORGANIZATION; NETWORK-ON-CHIP(NOC); NOC ARCHITECTURES; ROUTING RESOURCES; SILICON INTERPOSERS;

NETWORK-ON-CHIP;

EID: 84937721572     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2014.61     Document Type: Conference Paper

References (54)

1. D. Abts, N. Enright Jerger, J. Kim, D. Gibson, and M. Lipasti, "Achieving predictable performance through better memory controller placement in many-core CMPs," in Intl. Symp. on Computer Architecture, 2009.
2. K. Athikulwongse, A. Chakraborty, J.-S. Yang, D. Z. Pan, and S. K. Lim, "Stress-Driven 3D-IC Placement with TSV Keep-Out Zone and Regularity Study," in Intl. Conf. on Computer-Aided Design, San Jose, CA, November 2010, pp. 669-674.
3. M. Badr and N. Enright Jerger, "SynFull: Synthetic traffic models capturing a full range of cache coherence behaviour," in Intl. Symp. on Computer Architecture, June 2014.
4. A. Bakhoda, J. Kim, and T. Aamodt, "Throughput-Effective On-Chip Networks for Manycore Accelerators," in 43rd Intl. Symp. on Microarchitecture, Atlanta, GA, December 2010, pp. 421-432.
5. J. Balfour and W. J. Dally, "Design tradeoffs for tiled CMP on-chip networks," in Intl. Conf. on Supercomputing, 2006.
6. V. E. Benes, "Optimal Rearrangeable Multistage Connecting Networks," Bell System Technical Journal, vol. 43, pp. 1641-1656, 1964.
7. C. Bienia, "Benchmarking Modern Processors," Ph.D. dissertation, Princeton University, 2011.
8. N. Binkert et al., "gem5: A Multiple-ISA Full System Simulator with Detailed Memory Model," Computer Architecture News, vol. 39, June 2011.
9. B. Black, "Die Stacking is Happening," in Intl. Symp. on Microarchitecture, Davis, CA, December 2013.
10. B. Black et al., "Die-Stacking (3D) Microarchitecture," in MICRO-39, 2006.
11. C. Clos, "A Study of Non-Blocking Switching Networks," The Bell System Technical Journal, vol. 38, no. 5, pp. 406-424, March 1953.
12. J. Cong and Y. Zhang, "Thermal-Driven Multilevel Routing for 3-D ICs," in 10th Asia South Pacific Design Automation Conference, Shanghai, China, January 2005.
13. W. J. Dally, "Express cubes: Improving the performance of k-ary n-cube interconnection networks," IEEE Transactions on Computers, vol. 40, no. 9, pp. 1016-1023, 1991.
14. R. Das, S. Narayanasamy, S. K. Satpathy, and R. Dreslinski, "Catnap: Energy proportional multiple network-on-chip," in Intl. Symp. on Computer Architecture, 2013.
15. Y. Deng and W. Maly, "Interconnect Characteristics of 2.5-D System Integration Scheme," in Intl. Symp. on Physical Design, Sonoma County, CA, April 2001, pp. 171-175.
16. X. Dong, Y. Xie, N. Muralimanohar, and N. P. Jouppi, "Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support," in SC, 2010.
17. B. Grot, J. Hestness, S. W. Keckler, and O. Mutlu, "Express Cube Topologies for On-Chip Interconnects," in Intl. Symp. on High Performance Computer Architecture, Raleigh, NC, February 2009.
18. J.-H. Huang, "NVidia GPU Technology Conference: Keynote," Tech. Rep., March 2013.
19. R. Huemoeller, "Through Silicon Via (TSV) Product Technology," Amkor Technology, Tech. Rep., February 2012, Presented to IMAPS North Carolina Chapter.
20. W.-L. Hung, G. Link, Y. Xie, N. Vijaykrishnan, and M. J. Irwin, "Interconnect and Thermal-aware Floorplanning for 3D Microprocessors," in 7th Intl. Symp. on Quality Electronic Design, San Jose, CA, March 2006.
21. Institute of Microelectronics, "Process Design Kit (PDF) for 2.5D Through Silicon Interposer (TSI) Design Enablement & 2.5D TSI Cost Modeling," August 2012.
22. M. Jackson, "A Silicon Interposer-based 2.5D-IC Design Flow, Going 3D by Evolution Rather than by Revolution," Synopsis Insight Newsletter, Tech. Rep., 2012, issue 1.
23. JEDEC, "Wide I/O Single Data Rate (Wide I/O SDR)," http://www.jedec.org/standards-documents/docs/jesd229.
24. N. Jiang et al., "A detailed and flexible cycle-accurate networkon-chip simulator," in Intl. Symp. on Performance Analysis of Systems and Software, 2013.
25. T. H. Kgil et al., "PicoServer: Using 3D Stacking Technology to Enable a Compact Energy Efficient Chip Multiprocessor," in 12th Symp. on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, October 2006, pp. 117-128.
26. G. Kim, J. Kim, J.-H. Ahn, and J. Kim, "Memory-centric system interconnect design with hybrid memory cubes," in Intl. Conf. on Parallel Architectures and Compilation Techniques, 2013.
27. J.-S. Kim et al., "A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4x128 I/Os Using TSV-Based Stacking," in ISSCC, 2011.
28. J. Kim, J. Balfour, and W. J. Dally, "Flattened Butterfly Topology for On-Chip Networks," in Intl. Symp. on Microarchitecture, Chicago, IL, December 2007.
29. J. Kim, W. J. Dally, and D. Abts, "Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks," in Intl. Symp. on Computer Architecture, San Diego, CA, June 2007.
30. J. Kim, W. J. Dally, B. Towles, and A. K. Gupta, "Microarchitecture of a high-radix router," in Intl. Symp. on Computer Architecture, Boston, MA, June 2006.
31. J. Kim et al., "A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures," in 34th Intl. Symp. on Computer Architecture, San Diego, CA, June 2007.
32. M. M. Kim, J. D. Davis, M. Oskin, and T. Austin, "Polymorphic on-chip networks," in Intl. Symp. on Computer Architecture, 2008.
33. M. M. Kim, M. Mehrara, M. Oskin, and T. Austin, "Architectural implications of brick and mortar silicon manufacturing," in Intl. Symp. on Computer Architecture, 2007.
34. M. M. Lee, J. Kim, D. Abts, M. Marty, and J. W. Lee, "Probabilistic Distance-Based Arbitration: Providing Equality
35. M. M. Lee, J. Kim, D. Abts, M. Marty, and J. W. Lee, "Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs," in 43rd Intl. Symp. on Microarchitecture, Atlanta, GA, December 2010, pp. 509-519.
36. C. Leiserson, "Fat-trees: Universal networks for hardware efficient supercomputing," IEEE Transactions on Computers, vol. 34, no. 10, pp. 892-901, 1985.
37. F. Li et al., "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory," in 33rd Intl. Symp. on Computer Architecture, Boston, MA, June 2006, pp. 130-141.
38. C. C. Liu, I. Ganusov, M. Burtscher, and S. Tiwari, "Bridging the Processor-Memory Performance Gap with 3D IC Technology," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 556-564, November-December 2005.
39. G. H. Loh, "3D-Stacked Memory Architectures for Multi-Core Processors," in ISCA-35, 2008.
40. G. L. Loi, B. Agarwal, N. Srivastava, S.-C. Lin, and T. Sherwood, "A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy," in 43rd Design Automation Conference, San Francisco, CA, July 2006, pp. 991-996.
41. P. Lotfi-Kamran, B. Grot, and B. Falsafi, "NOC-Out: Microarchitecting a Scale-Out Processor," in Intl. Symp. on Microarchitecture, Vancouver, BC, December 2012, pp. 177-187.
42. R. Morris, A. K. Kodi, and A. Louri, "3D-NoC: Reconfigurable 3D Photonic On-Chip Interconnect for Multicoresj," in Intl. Conf. on Computer Design, Montreal, Canada, September 2012, pp. 413-418.
43. C. Okoro et al., "Analysis of the Induced Stresses in Silicon During Thermocompression Cu-Cu Bonding of Cu-Through-Vias in 3D-SIC Architecture," in the Electronic Components and Technology Conference, Reno, NV, May 2007, pp. 249-255.
44. D. Park et al., "MIRA: A Multi-layered On-chip Interconnect Router Architecture," in Intl. Symp. on Computer Architecture, Beijing, China, June 2008, pp. 251-261.
45. K. Puttaswamy and G. H. Loh, "Thermal Analysis of a 3D Die-Stacked High-Performance Microprocessor," in ACM Great Lakes Symp. on VLSI, Philadelphia, PA, May 2006, pp. 19-24.
46. K. Saban, "Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency," Xilinx, White Paper, 2011, wP380 (v1.1).
47. M. Santarini, "Stacked & Loaded: Xilinx SSI, 28-Gbps I/O Yield Amazing FPGAs," Xilinx Xcell Journal, Tech. Rep., First Quarter 2011.
48. C. Sun et al., "DSENT - a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling," in NOCS, May 2012.
49. S. Volos et al., "CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache Coherent Servers," in 6th NOCS, Lyngby, Denmark, May 2012, pp. 67-74.
50. D. Wentzlaff et al., "On-chip interconnection architecture of the Tile Processor," Micro, IEEE, vol. 27, no. 5, pp. 15-31, Sept.-Oct. 2007.
51. Y. Xie, G. H. Loh, B. Black, and K. Bernstein, "Design Space Exploration for 3D Architecture," ACM Journal of Emerging Technologies in Computer Systems, vol. 2, no. 2, pp. 65-103, April 2006.
52. Y. Xu et al., "A Low-radix and Low-diameter 3D Interconnection Network Design," in 15th Intl. Symp. on High Performance Computer Architecture, Raleigh, NC, February 2009, pp. 30-42.
53. Y. J. Yoon, N. Concer, M. Petracca, and L. Carloni, "Virtual channels vs. multiple physical networks: a comparative analysis," in Design Automation Conference, 2010.
54. A. Zia, S. Kannan, G. Rose, and H. J. Chao, "Highly-scalable 3D Clos NoC for Many-core CMPs," in NEWCAS Conference, Montreal, Canada, June 2010, pp. 229-232.