A 1.2V 12.8GB/s 2Gb mobile wide-I/O DRAM with 4x128 I/Os using TSV-based stacking

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 496-497

  Kim, Jung Sik ^a   Oh, Chi Sung ^a   Lee, Hocheol ^a   Lee, Donghyuk ^a   Hwang, Hyong Ryol ^a   Hwang, Sooman ^a   Na, Byongwook ^a   Moon, Joungwook ^a   Kim, Jin Guk ^a   Park, Hanna ^a   Ryu, Jang Woo ^a   Park, Kiwon ^a   Kang, Sang Kyu ^a   Kim, So Young ^a   Kim, Hoyoung ^a   Bang, Jong Min ^a   Cho, Hyunyoon ^a   Jang, Minsoo ^a   Han, Cheolmin ^a   Lee, Jung Bae ^a   Kyung, Kyehyun ^a   Choi, Joo Sun ^a   Jun, Young Hyun ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION;

DATA BANDWIDTH; DATA RATES; HIGH CAPACITY; HIGH SPEED; LOW-POWER CONSUMPTION; MARKET TRENDS; MOBILE DRAM; PORTABLE ELECTRONIC DEVICES;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 79955711352     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746413     Document Type: Conference Paper

References (4)

1. IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std. 1149.1-2001, 2001.
2. Y. Idei, et al., "Dual-Period Self-Refresh Scheme for Low-Power DRAM's with On-Chip PROM Mode Register," IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 253-259, Feb. 1998.
3. J. Kim and M. C. Papaefthymiou, "Block-Based Multiperiod Dynamic Memory Design for Low Data-Retention Power," IEEE Trans. VLSI Systems, vol. 11, no. 6, pp. 1006-1018, Dec. 2003.
4. J.-H. Ahn, et al., "Adaptive Self Refresh Scheme for Battery Operated High-Density Mobile DRAM Applications," Proc. ASSCC, pp. 319-322, Nov. 2006.