Memory-centric system interconnect design with Hybrid Memory Cubes

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2013, Pages 145-155

  Kim, Gwangsun ^a   Kim, John ^a   Ahn, Jung Ho ^b   Kim, Jaeha ^b  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Seoul National University   (South Korea)

Author keywords

Hybrid Memory Cube; Memory bandwidth wall; Memory network; Processor interconnect

Indexed keywords

HYBRID MEMORY; INTERCONNECT DESIGN; MEMORY BANDWIDTHS; MEMORY NETWORK; MICRO ARCHITECTURES; NETWORK DIAMETER; PERFORMANCE BOTTLENECKS; PROCESSOR INTERCONNECT;

BANDWIDTH; COMPUTER ARCHITECTURE; DISTRIBUTED COMPUTER SYSTEMS; ENERGY EFFICIENCY; GEOMETRY; NETWORK ARCHITECTURE; PARALLEL ARCHITECTURES;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84887466693     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2013.6618812     Document Type: Conference Paper

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