Die stacking (3D) microarchitecture

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2006, Pages 469-479

  Black, Bryan ^a   Annavaram, Murali ^a   Brekelbaum, Ned ^a   Devale, John ^a   Lei, Jiang ^a   Loh, Gabriel H ^a   McCauley, Don ^a   Morrow, Pat ^a   Nelson, Donald W ^a   Pantuso, Daniel ^a   Reed, Paul ^a   Rupley, Jeff ^a   Shankar, Sadasivan ^a   John, Shen ^a   Webb, Clair ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR CHIPS; THREE DIMENSIONAL; TRANSISTORS;

DIE STACKING; POWER REDUCTION; VOLTAGE SCALING;

NETWORK ARCHITECTURE;

EID: 40349090128     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2006.18     Document Type: Conference Paper

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