MIRA: A multi-layered on-chip interconnect router architecture

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2008, Pages 251-261

  Park, Dongkook ^a   Eachempati, Soumya ^a   Das, Reetuparna ^a   Mishra, Asit K ^a   Xie, Yuan ^a   Vijaykrishnan, N ^a   Das, Chita R ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; BEHAVIORAL RESEARCH; COMPUTER ARCHITECTURE; COMPUTER SCIENCE; COMPUTER SYSTEMS; COMPUTERS; CONSERVATION; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; INTERCONNECTION NETWORKS; OPTICAL INTERCONNECTS; TECHNOLOGY; THREE DIMENSIONAL;

3D DESIGN; AVERAGE LATENCY; CYCLE-ACCURATE; DEEP SUB MICRON TECHNOLOGIES; ENERGY-EFFICIENT; INTERCONNECT DELAYS; INTERNATIONAL SYMPOSIUM; LAYER 3; MULTI CORES; MULTI-LAYERED; MULTIPLE LAYERS; NETWORK-ON-CHIP; NOC ARCHITECTURES; NOC DESIGN; NOC ROUTERS; ON-CHIP INTERCONNECTS; POWER ANALYSIS; POWER CONSUMPTION; POWER MODELING; ROUTER ARCHITECTURES; SIMULATION RESULTS; SYNTHETIC WORKLOADS; THREE-DIMENSIONAL INTEGRATION;

ROUTERS;

EID: 52649135185     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2008.13     Document Type: Conference Paper

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