Thermal analysis of a 3D die-stacked high-performance microprocessor

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn 2006, Issue , 2006, Pages 19-24

  Puttaswamy, Kiran ^a   Loh, Gabriel H ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Georgia Institute of Technology   (United States)

Author keywords

3D Technology; Power density; Thermals

Indexed keywords

DIES; HEAT LOSSES; HEAT SINKS; INTEGRATED CIRCUITS; THERMAL EFFECTS;

3D TECHNOLOGY; POWER CONSUMPTION; POWER DENSITY; THERMALS;

MICROPROCESSOR CHIPS;

EID: 33750922540     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1127908.1127915     Document Type: Conference Paper

References (33)

1. J. W. Joyner, R. Venkatesan, P. Zarkesh-Ha, J. A. Davis, and J. D. Meindl, "Impact of three-dimensional architectures on interconnects in gigascale integration," IEEE Transactions on VLSI, vol. 9, no. 6, pp. 922-928, Dec 2001.
2. K. Puttaswamy and G. H. Loh, "Implementing Caches in a 3D Technology for High Performance Processors," in Proceedings of the International Conference on Computer Design, San Jose, CA, USA, October 2005.
3. Y.-F. Tsai, Y. Xie, N. Vijaykrishnan, and M. J. Irwin, "Three-Dimensional Cache Design Using 3DCacti," in Proceedings of the International Conference on Computer Design, San Jose, CA, USA, October 2005.
4. K. Puttaswamy and G. H. Loh, "Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology," in Proceedings of the International Symposium on VLSI, Karlsruhe, Germany, March 2006.
5. J. W. Joyner and J. D. Meindl, "Opportunities for reduced power dissipation using three-dimensional integration," in Proceedings of the International Interconnect Technology Conference, 2002, pp. 148-150.
6. S. Borkar, "Design Challenges of Technology Scaling," IEEE Micro Magazine, vol. 19, no. 4, pp. 23-29, July 1999.
7. D. Brooks, P. W. Cook, P. Bose, S. E. Schuster, H. Jacobson, P. N. Kudva, A. Buyuktosunoglu, J.-D. Wellman, V. Zyuban, and M. Gupta, "Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors," IEEE Micro Magazine, vol. 20, no. 6, pp. 26-44, November 2000.
8. B. Black, D. Nelson, C. Webb, and N. Samra, "3D Processing Technology and its Impact on IA32 Microprocessors," in Proceedings of the 22nd International Conference on Computer Design, San Jose, CA, USA, October 2004, pp. 316-318.
9. K. W. Guarini, A. W. Topol, M. Ieong, R. Yu, L. Shi, M. R. Newport, D. J. Frank, D. V. Singh, G. M. Cohen, S. V. Nitta, D. C. Boyd, P. A. O'Neil, S. L. Tempest, H. B. Pogge, S. Purushothaman, and W. E. Haensch, "Electrical Integrity of State-of-the-Art 0.13μm SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication," in Proceedings of the International Electron Devices Meeting, December 2002, pp. 943-945.
10. D. Nelson, C. Webb, D. McCauley, K. Raol, J. R. II, J. DeVale, and B. Black, "A 3D Interconnect Methodology Applied to iA32-class Architectures for Performance Improvements through RC Mitigation," in Proceedings of the 21st International VLSI Multilevel Interconnection Conference. Waikoloa Beach, HI, USA, September 2004.
11. P. Reed, G. Yeung, and B. Black, "Design Aspects of a Microprocessor Data Cache using 3D Die Interconnect Technology," in Proceedings of the International Conference on Integrated Circuit Design and Technology, Austin, TX, USA, May 2005, pp. 15-18.
12. L. Cheng, L. Deng, and M. Wong, "Floorplan Design for 3-D VLSI Design," in Proceedings of the Asia South Pacific Design Automation Conference, Shanghai, China, January 2005.
13. J. Gong and Y. Zhang, "Thermal-Driven Multilevel Routing for 3-D ICs," in Proceedings of the Asia South Pacific Design Automation Conference, Shanghai, China, January 2005.
14. S. Das, A. Fan, K.-N. Chen, and C. S. Tan, "Technology, Performance, and Computer-Aided Design of Three-Dimensional Integrated Circuits," in Proceedings of the International Symposium on Physical Design, Phoenix, AZ, USA, April 2004, pp. 108-115.
15. B. Goplen and S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs Using a Force Directed Approach," in Proceedings of the International Conference on Computer-Aided Design, San Jose, CA, USA, November 2003, pp. 81-85.
16. S. K. Lim, "Physical design for 3D system on package," IEEE Design & Test of Computers, vol. 22, no. 6, pp. 532-539, Nov.-Dec 2005.
17. A. Rahman and R. Reif, "System Level Performance Evaluation of Three-Dimensional Integrated Circuits," IEEE Transactions on VLSI, vol. 8, no. 6, pp. 671-678, June 2000.
18. S. Das, A. Chandrakasan, and R. Reif, "Timing, energy, and thermal performance of three-dimensional integrated circuits," in GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI, 2004, pp. 338-343.
19. P. Morrow, M. J. Kobrinsky, S. Ramanathan, C.-M. Park, M. Harmes, V. Ramachandrarao, H. mog Park, G. Kloster, S. List, and S. Kim, "Wafer-Level 3D Interconnects Via Cu Bonding," in Proceedings of the 21st Advanced Metallization Conference, San Diego, CA, USA, October 2004.
20. R. Reif, A. Fan, K.-N. Chen, and S. Das, "Fabrication Technologies for Three-Dimensional Integrated Circuits," in Proceedings of the 3rd International Symposium on Quality Electronic Design, San Jose, CA, USA, March 2002, pp. 33-37.
21. E. C. Samson, S. V. Machiroutu, J.-Y. Chang, I. Santos, J. Hermerding, A. Dani, R. Prasher, and D. W. Song, "Interface Material Selection and a Thermal Management Technique in Second-Generation Platforms Built on Intel Centrino Mobile Technology," Intel Technology Journal, vol. 9, no. 1, February 2005.
22. S. Gupta, M. Hubert, S. Hong, and R. Patti, "Techniques for Producing 3D ICs with High-Density Interconnect," in Proceedings of the 21st International VLSI Multilevel Interconnection Conference, Waikoloa Beach, HI, USA, September 2004.
23. Tezzaron Semiconductor, "WWW Site," http://www.tezzaron.com.
24. Berkeley Predictive Technology Model, "WWW Site," http://www-device.eecs.berkeley.edu/ptm.
25. K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, and D. Tarjan, "Temperature-Aware Microarchitecture: Modeling and Implementation," Transactions on Architecture and Code Optimization, vol. 1, no. 1, pp. 94-125, March 2004.
26. CRC Press, "CRC Handbook of Chemistry," http://www.hbcpnetbase. com/.
27. T.-Y. Chiang, S. J. Souri, C. O. Chui, and K. C. Saraswat, "Thermal analysis of heterogeneous 3D ICs with various integration scenarios," in International IEDM Technical Digest, 2001, pp. 31.2.1-31.2.4.
28. S. Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs," in International IEDM Technical Digest, Dec 2000, pp. 727-730.
29. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: a framework for architectural-level power analysis and optimizations," in Proceedings of the 27th annual international symposium on Computer architecture, 2000, pp. 83-94.
30. G. Sery, S. Borkar, and V. De, "Life is cmos: why chase the life after?" in Proceedings of the 39th conference on Design automation, 2002, pp. 78-83.
31. R. S. Prasher, J.-Y. Chang, I. Sauciuc, S. Narasimhan, D. Chau, G. Chrysler, A. Myers, S. Prstic, and C. Hu, "Nano and Micro Technology-Based Next-Generation Package-Level Cooling Solutions," Intel Technology Journal, vol. 9, no. 4, November 2005.
32. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-Aware Microarchitecture," in Proceedings of the 30th International Symposium on Computer Architecture, May 2003, pp. 2-13.
33. International Technology Roadmap for Semiconductors, "WWW Site," http://public.itrs.net.