CCNoC: Specializing on-chip interconnects for energy efficiency in cache-coherent servers

Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012

Volumn , Issue , 2012, Pages 67-74

  Volos, Stavros ^a   Seiculescu, Ciprian ^a   Grot, Boris ^a   Pour, Naser Khosro ^a   Falsafi, Babak ^a   De Micheli, Giovanni ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ASYMMETRIC NETWORKS; CACHE COHERENCE; CHIP DESIGN; CHIP MULTIPROCESSOR; CONTROL MESSAGES; DATA PATHS; ENERGY EFFICIENT; FLOW CONTROL STRATEGY; FUTURE TECHNOLOGIES; MANY CORE; MICRO ARCHITECTURES; MOORE'S LAW; NETWORK ON CHIP; NOC DESIGN; ON CHIPS; ON-CHIP INTERCONNECTS; ON-CHIP NETWORKS; PERFORMANCE LEVEL; PERFORMANCE OBJECTIVE; PERFORMANCE SCALABILITY; POWER EFFICIENCY; SUPPLY VOLTAGES;

COMPUTER ARCHITECTURE; DESIGN; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS; ROUTERS; VLSI CIRCUITS;

NETWORK ARCHITECTURE;

EID: 84862742430     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2012.15     Document Type: Conference Paper

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