3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2012, Pages 413-418

  Morris, Randy ^a   Kodi, Avinash Karanth ^a   Louri, Ahmed ^b  

^a US Institute of Navigation   (United States)

^b University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING; CHANNEL BANDWIDTH; COMMUNICATION BANDWIDTH; DISRUPTIVE TECHNOLOGY; HIGH-PERFORMANCE INTERCONNECT; INTERCONNECT TECHNOLOGY; LOW-POWER DISSIPATION; MANY-CORE; METALLIC INTERCONNECTS; MULTI-CORES; MULTICORE ARCHITECTURES; ON CHIP INTERCONNECT; PERFORMANCE LIMITATIONS; POWER EFFICIENT; TECHNOLOGY SOLUTIONS;

BENCHMARKING; COMMUNICATION; NANOPHOTONICS; SOFTWARE ARCHITECTURE; TELECOMMUNICATION SYSTEMS;

THREE DIMENSIONAL COMPUTER GRAPHICS;

EID: 84872092518     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2012.6378672     Document Type: Conference Paper

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