Probabilistic distance-based arbitration: Providing equality of service for many-core CMPs

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 509-519

  Lee, Michael M ^a   Kim, John ^a   Abts, Dennis ^b   Marty, Michael ^b   Lee, Jae W ^c  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b GOOGLE INC   (United States)

^c Parakinetics Inc   (United States)

Author keywords

Age based arbitration; Fairness; On chip network; Quality of service (QoS)

Indexed keywords

AGE-BASED; CHIP MULTIPROCESSOR; COMMON RESOURCES; DIFFERENTIATED SERVICES; DISTANCE-BASED; FAIRNESS; MAIN MEMORY; MANY-CORE; ON CHIP INTERCONNECT; ON CHIPS; ON-CHIP NETWORK; POINT-TO-POINT LINK; PROBABILISTIC DISTANCE; PROCESSING CORE; QUALITY OF SERVICE (QOS); ROUND ROBIN; SHARED RESOURCES; STABLE NETWORK; TRAFFIC PATTERN; VIRTUAL CHANNELS;

QUALITY CONTROL; QUALITY OF SERVICE; ROUTERS;

TELECOMMUNICATION SERVICES;

EID: 79951719950     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.18     Document Type: Conference Paper

References (25)

1. J. W. Lee, M. C. Ng, and K. Asanovic, "Globally-synchronized frames for guaranteed quality-of-service in on-chip networks," in ISCA, Beijing, China, 2008, pp. 89-100.
2. B. Grot, S. W. Keckler, and O. Mutlu, "Preemptive virtual clock: A flexible, efficient, and cost-effective qos scheme for networks-on-a-chip," in MICRO, New York, NY, 2009.
3. D. Stiliadis and A. Varma, "Design and analysis of frame-based fair queueing: a new traffic scheduling algorithm for packet-switched networks," in SIGMETRICS, Philadelphia, PA, 1996, pp. 104-115. (Pubitemid 126549544)
4. D. Abts, N. D. Enright Jerger, J. Kim, D. Gibson, and M. H. Lipasti, "Achieving predictable performance through better memory controller placement in many-core cmps," in ISCA, Austin, TX, 2009.
5. D. Abts and D. Weisser, "Age-based packet arbitration in large-radix k-ary n-cubes," in SC '07, 2007.
6. W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. San Francisco, CA: Morgan Kaufmann, 2004.
7. C. Bienia, S. Kumar, J. P. Singh, and K. Li., "The PARSEC Benchmark Suite: Characterization and Architectural Implications," in PACT, 2008.
8. M. M. K. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood, "Multifacet's general execution-driven multiprocessor simulator (gems) toolset," SIGARCH Comp. Arch. News, vol. 33, no. 4, pp. 92-99, 2005.
9. A. Demers, S. Keshav, and S. Shenker, "Analysis and simulation of a fair queueing algorithm," in SIGCOMM, Austin, Texas, 1989, pp. 1-12. (Pubitemid 20692629)
10. S. Vangal et al., "An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS," ISSCC, pp. 98-589, Feb. 2007.
11. P. Gratz, C. Kim, R. McDonald, S. Keckler, and D. Burger, "Implementation and Evaluation of On-Chip Network Architectures," in ICCD, 2006.
12. D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C.-C. Miao, J. Brown, and A. Agarwal, "On-chip interconnection architecture of the tile processor," IEEE Micro, vol. 27, no. 5, pp. 15-31, Sept.-Oct. 2007. (Pubitemid 350218384)
13. H. Wang, L. S. Peh, and S. Malik, "Power-driven Design of Router Microarchitectures in On-chip Networks," in MICRO, 2003.
14. A. Kumar, P. Kundu, A. Singh, L.-S. Peh, and N. Jha, "A 4.6tbits/s 3.6ghz single-cycle noc router with a novel switch allocator in 65nm cmos," in ICCD, October 2007.
15. L.-S. Peh and W. J. Dally, "A delay model and speculative architecture for pipelined routers," in HPCA, 2001.
16. C. A. Waldspurger and W. E. Weihl, "Lottery scheduling: flexible proportional-share resource management," in OSDI, 1994.
17. K. Lahiri, A. Raghunathan, and G. Lakshminarayana, "Lotterybus: a new high-performance communication architecture for system-on-chip designs," in DAC, Las Vegas, Nevada, 2001, pp. 15-20. (Pubitemid 32840919)
18. I. Hur and C. Lin, "Adaptive history-based memory schedulers," in MICRO, 2004, pp. 343-354. (Pubitemid 40927709)
19. R. Das, O. Mutlu, T. Moscibroda, and C. R. Das, "Aérgia: exploiting packet latency slack in on-chip networks," in ISCA, Saint-Malo, France, 2010, pp. 106-116.
20. J. H. Kim and A. A. Chien, "Rotating Combined Queueing (RCQ): Bandwidth and latency guarantees in low-cost, high-performance networks," in ISCA, Philadelphia, PA, 1996, pp. 226-236.
21. K. Goossens, J. Dielissen, and A. Radulescu, "Æthereal network on chip: Concepts, architectures, and implementations," IEEE Des. Test, vol. 22, no. 5, pp. 414-421, 2005. (Pubitemid 41522729)
22. W.-D. Weber, J. Chou, I. Swarbrick, and D. Wingard, "A quality-ofservice mechanism for interconnection networks in system-on-chips, " in DATE, Munich, Germany, 2005, pp. 1232-1237. (Pubitemid 44172178)
23. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "QNoC: QoS architecture and design process for network on chip," J. Syst. Archit., vol. 50, no. 2-3, pp. 105-128, 2004.
24. L. Zhang, "Virtual Clock: a new traffic control algorithm for packet switching networks," in SIGCOMM, Philadelphia, PA, 1990, pp. 19-29.
25. K. H. Yum, E. J. Kim, C. R. Das, and A. S. Vaidya, "MediaWorm: A QoS capable router architecture for clusters," IEEE Trans. Parallel Distrib. Syst., vol. 13, no. 12, pp. 1261-1274, 2002.