NOC-Out: Microarchitecting a scale-out processor

Proceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012

Volumn , Issue , 2012, Pages 177-187

  Lotfi Kamran, Pejman ^a   Grot, Boris ^a   Falsafi, Babak ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

INTER-CORE COMMUNICATIONS; INTERCONNECT FABRICS; KEY CHARACTERISTICS; LASTLEVEL CACHES (LLC); MANY-CORE PROCESSORS; NETWORK CONNECTIVITY; PERFORMANCE LIMITATIONS; TREE-BASED TOPOLOGIES;

COMPUTER ARCHITECTURE; DESIGN; TOPOLOGY;

COMPLEX NETWORKS;

EID: 84876533349     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2012.25     Document Type: Conference Paper

References (22)

1. A. Bakhoda, J. Kim, and T. M. Aamodt, "Throughput-Effective On-Chip Networks for Manycore Accelerators," in International Symposium on Microarchitecture, December 2010, pp. 421-432.
2. J. D. Balfour and W. J. Dally, "Design Tradeoffs for Tiled CMP On-Chip Networks," in International Conference on Supercomputing, June 2006, pp. 187-198.
3. "CloudSuite 1.0," 2012. [Online]. Available: http://parsa.epfl. ch/cloudsuite
4. M. Ferdman, A. Adileh, O. Kocberber, S. Volos, M. Alisafaee, D. Jevdjic, C. Kaynak, A. D. Popescu, A. Ailamaki, and B. Falsafi, "Clearing the Clouds: A Study of Emerging Scale-Out Workloads on Modern Hardware," in International Conference on Architectural Support for Programming Languages and Operating Systems, March 2012, pp. 37-48.
5. "Global Server Hardware Market 2010-2014," March 2011. [Online]. Available: http://www.technavio.com/content/global-server-hardware- market-2010-2014
6. B. Grot, D. Hardy, P. Lotfi-Kamran, B. Falsafi, C. Nicopoulos, and Y. Sazeides, "Optimizing Data-Center TCO with Scale-Out Processors," IEEE Micro, vol. 32, no. 5, pp. 52-63, September/October 2012.
7. B. Grot, J. Hestness, S.W. Keckler, and O. Mutlu, "Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees," in International Symposium on Computer Architecture, June 2011, pp. 268-279.
8. N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki, "Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches," in International Symposium on Computer Architecture, June 2009, pp. 184-195.
9. J. Huh, C. Kim, H. Shafi, L. Zhang, D. Burger, and S.W. Keckler, "A NUCA Substrate for Flexible CMP Cache Sharing," in International Conference on Supercomputing, June 2005, pp. 31-40.
10. "International Technology Roadmap for Semiconductors (ITRS), 2011 Edition." [Online]. Available: http://www.itrs. net/Links/2011ITRS/ Home2011.htm
11. A. Kahng, B. Li, L.-S. Peh, and K. Samadi, "ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration," in Design, Automation, and Test in Europe, April 2009, pp. 423-428.
12. J. Kim, "Low-Cost Router Microarchitecture for On-Chip Networks," in International Symposium on Microarchitecture, December 2009, pp. 255-266.
13. J. Kim, J. Balfour, and W. Dally, "Flattened Butterfly Topology for On-Chip Networks," in International Symposium on Microarchitecture, December 2007, pp. 172-182.
14. P. Lotfi-Kamran, M. Ferdman, D. Crisan, and B. Falsafi, "TurboTag: Lookup Filtering to Reduce Coherence Directory Power," in International Symposium on Low Power Electronics and Design, August 2010, pp. 377-382.
15. P. Lotfi-Kamran, B. Grot, M. Ferdman, S. Volos, O. Kocberber, J. Picorel, A. Adileh, D. Jevdjic, S. Idgunji, E. Ozer, and B. Falsafi, "Scale-Out Processors," in International Symposium on Computer Architecture, June 2012, pp. 500-511.
16. G. Michelogiannakis, J. Balfour, andW. Dally, "Elastic-Buffer Flow Control for On-Chip Networks," in International Symposium on High-Performance Computer Architecture, February 2009, pp. 151-162.
17. T. Moscibroda and O. Mutlu, "A Case for Bufferless Routing in On-Chip Networks," in International Symposium on Computer Architecture, June 2009, pp. 196-207.
18. N. Muralimanohar, R. Balasubramonian, and N. Jouppi, "Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0," in International Symposium on Microarchitecture, December 2007, pp. 3-14.
19. "Tilera TILE-Gx." [Online]. Available: http://www.tilera.com/ products/TILE-Gx.php
20. S. Volos, C. Seiculescu, B. Grot, N. Khosro Pour, B. Falsafi, and G. De Micheli, "CCNoC: Specializing On-Chip Interconnects for Energy Efficiency Cache-Coherent Servers," in International Symposium on Networks-on-Chips, May 2012, pp. 67-74.
21. H. Wang, L.-S. Peh, and S. Malik, "Power-driven Design of Router Microarchitectures in On-chip Networks," in International Symposium on Microarchitecture, December 2003, pp. 105-116.
22. T. Wenisch, R. Wunderlich, M. Ferdman, A. Ailamaki, B. Falsafi, and J. Hoe, "SimFlex: Statistical Sampling of Computer System Simulation," IEEE Micro, vol. 26, no. 4, pp. 18-31, July/August 2006.