A novel approach to hedge and compensate the critical dimension variation of the developed-and-etched circuit patterns for yield enhancement in semiconductor manufacturing

Computers and Operations Research

Volumn 53, Issue , 2015, Pages 309-318

  Chien, Chen Fu ^a   Chen, Ying Jen ^a   Hsu, Chia Yu ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b YUAN ZE UNIVERSITY   (Taiwan)

Author keywords

Critical dimension; Feed forward control; Manufacturing intelligence; Run to run (R2R); Tool affinity; Tool dispatching; Yield enhancement

Indexed keywords

ETCHING; PHOTOLITHOGRAPHY; SEMICONDUCTOR DEVICE MANUFACTURE; TIMING CIRCUITS; WOODEN FENCES;

ADVANCED EQUIPMENT CONTROL; ADVANCED PROCESS CONTROL; CRITICAL DIMENSION; CRITICAL DIMENSION VARIATIONS; RUN-TO-RUN; SEMICONDUCTOR MANUFACTURING; TOOL DISPATCHING; YIELD ENHANCEMENT;

PROCESS CONTROL;

EID: 84912535250     PISSN: 03050548     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.cor.2014.05.009     Document Type: Article

References (47)

1. G.E. Moore Cramming more components onto integrated circuits Electron Mag 38 8 1965 114 117
2. G.S. May, and C.J. Spanos Fundamentals of semiconductor manufacturing and process control 2006 John Wiley & Sons Hoboken, NJ
3. C.-F. Wu, C.-M. Hung, J.-H. Chen, and A.-C. Lee Advanced process control of the critical dimension in photolithography Int J Precis Eng Manuf 9 1 2008 12 18
4. Z. Mao, and W. Kang Benchmark study of run-to-run controllers for the lithographic control of the critical dimension J Micro/Nanolithogr, MEMS and MOEMS 6 2 2007 023001
5. B.R. Parkinson, H. Lee, M. Funk, D. Prager, A. Yamashita, and R. Sundararajan Addressing dynamic process changes in high volume plasma etch manufacturing by using multivariate process control IEEE Trans Semicond Manuf 23 2 2010 185 193
6. C. El Chemali, J. Freudenberg, M. Hankinson, W. Collison, and T. Ni Critical dimension control of a plasma etch process by integrating feedforward and feedback run-to-run control J Vac Sci Technol B: Microelectron Nanometer Struct 21 6 2003 2304
7. C. Peronis, and R. Patrick Targeting gate CD using feedforward APC and voltage control Solid State Technol 12 12 2003 59 62
8. W.K. Ho, A. Tay, M. Chen, J. Fu, H. Lu, and X. Shan Critical dimension uniformity via real-time photoresist thickness control IEEE Trans Semicond Manuf 20 4 2007 376 380
9. Q. Zhang, K. Poolla, and C.J. Spanos One step forward from run-to-run critical dimension control: across-wafer level critical dimension control through lithography and etch process J Process Control 18 10 2008 937 945
10. M. Nagase, and K. Tokashiki Advanced gate etching for accurate CD control for 130-nm node ASIC manufacturing IEEE Trans Semicond Manuf 17 3 2004 281 285
11. M. Kurihara, M. Izawa, Tanaka Ji, K. Kawai, and N. Fujiwara Gate CD control considering variation of Gate and STI structure IEEE Trans Semicond Manuf 20 3 2007 232 238
12. D.A. Williams, A.R. Locander, T. Herrera, J.D. Garza, and C.K. Parker Improvements in polysilicon etch bias and transistor gate control with module level APC methodologies IEEE Trans Semicond Manuf 18 4 2005 522 527
13. L. Monch, H. Balasubramanian, J.W. Fowler, and M.E. Pfund Heuristic scheduling of jobs on parallel batch machines with incompatible job families and unequal ready times Comput Oper Res 32 11 2005 2731 2750
14. Y.F. Lee, Z.B. Jiang, and H.R. Liu Multiple-objective scheduling and real-time dispatching for the semiconductor manufacturing system Comput Oper Res 36 3 2009 866 884
15. T.C. Chiang, and L.C. Fu Rule-based scheduling in wafer fabrication with due date-based objectives Comput Oper Res 39 11 2012 2820 2835
16. R.K. Nurani, R. Akella, and A.J. Strojwas In-line defect sampling methodology in yield management: an integrated framework IEEE Trans Semicond Manuf 9 4 1996 506 515
17. C.-F. Chien, K. Chang, and C. Chen Design of sampling strategy for measuring and compensating overlay errors in semiconductor manufacturing Int J Prod Res 41 11 2003 2547 2561
18. C.-F. Chien, and C. Hsu UNISON analysis to model and reduce step-and-scan overlay errors for semiconductor manufacturing J Intell Manuf 22 3 2011 399 412
19. M. Asano, and T. Ikeda Sampling plan optimization for critical dimension metrology J Microlithogr, Microfabr, Microsyst 5 3 2006 033008
20. T. Vincent, J. Stirton, and K. Poolla Metrology sampling strategies for process monitoring applications IEEE Trans Semicond Manuf 24 4 2011 489 498
21. S.W. Butler Process control in semiconductor manufacturing J Vac Sci Technol B 13 4 1995 1917 1923
22. J. Moyne, E. del Castillo, and A.M. Hurwitz Run-to-run control in semiconductor manufacturing 2001 CRC Press Boca Raton, Florida
23. J. Moyne, and B. Schulze Yield management enhanced advanced process control system (YMeAPC): Part I: description and case study of feedback for optimized multiprocess control IEEE Trans Semicond Manuf 23 2 2010 221 235
24. A. Chen, and R.S. Guo Age-based double EWMA controller and its application to CMP processes IEEE Trans Semicond Manuf 14 1 2001 11 19
25. R. Telfeyan, J. Moyne, N. Chaudhry, J. Pugmire, S. Shellman, and D. Boning A multilevel approach to the control of a chemical-mechanical planarization process J Vac Sci Technol A 14 3 1996 1907 1913
26. S. Qin, G. Cherry, R. Good, J. Wang, and C. Harrison Semiconductor manufacturing process control and monitoring: a fab-wide framework J Process Control 16 3 2006 179 191
27. S.R. Leang, S.-Y. Ma, J. Thomson, B.J. Bombay, and C.J. Spanos A control system for photolithographic sequences IEEE Trans Semicond Manuf 9 2 1996 191 207
28. S. Ruegsegger, A. Wagner, J.S. Freudenberg, and D.S. Grimard Feedforward control for reduced run-to-run variation in microelectronics manufacturing IEEE Trans Semicond Manuf 12 4 1999 493 502
29. N. Chaudhry, J. Moyne, and E.A. Rundensteiner Active controller: utilizing active databases for implementing multistep control of semiconductor manufacturing IEEE Trans Compon, Packag, Manuf Technol - Part C 21 3 1998 217 224
30. N. Jedidi, P. Sallagoity, A. Roussy, and S. Dauzere-Peres Feedforward run-to-run control for reduced parametric transistor variation in CMOS logic 0.13 mu m technology IEEE Trans Semicond Manuf 24 2 2011 273 279
31. C.-F. Chien, and C. Chen A novel timetabling algorithm for a furnace process for semiconductor fabrication with constrained waiting and frequency-based setups OR Spectr 29 3 2007 391 419
32. D.C. Montgomery Design and analysis of experiments 4th ed 1997 John Wiley & Sons New York
33. C.-F. Chien, and J. Zheng Mini-max regret strategy for robust capacity expansion decisions in semiconductor manufacturing J Intell Manuf 23 6 2012 2151 2159
34. C.-F. Chien, Y.-J. Chen, C.-Y. Hsu, and H.-K. Wang Overlay error compensation using advanced process control with dynamically adjusted proportional-integral R2R controller IEEE Trans Autom Sci Eng 11 2 2014 473 484
35. C.-F. Chien, C.-Y. Hsu, and P.-L. Chen Semiconductor fault detection and classification for yield enhancement and manufacturing intelligence Flex Serv Manuf J 25 3 2013 367 388
36. H. Hung, and A. Chen Test of covariance changes without a large sample and its application to fault detection and classification J Process Control 22 6 2012 1113 1121
37. C.-J. Kuo, C.-F. Chien, and C.-D. Chen Manufacturing intelligence to exploit the value of production and tool data to reduce cycle time IEEE Trans Autom Sci Eng 8 1 2013 103 111
38. H.-C. Yu, K.-Y. Lin, and C.-F. Chien Hierarchical indices to detect equipment condition changes with high dimensional data for semiconductor manufacturing J Intell Manuf 2014 (10.1007/s10845-013-0785-3)
39. C.-F. Chien, and C.-Y. Hsu A novel method for determining machine subgroups and backups with an empirical study for semiconductor manufacturing J Intell Manuf 17 4 2006 429 439
40. S.C. Sarin, A. Varadarajan, and L. Wang A survey of dispatching rules for operational control in wafer fabrication Prod Plann Control: Manag Oper 22 1 2011 4 24
41. D. Pyle Data preparation for data mining 1999 Morgan Kaufrnann San Francisco, CA
42. C.-F. Chien, and L.F. Chen Using rough set theory to recruit and retain high-potential talents for semiconductor manufacturing IEEE Trans Semicond Manuf 20 4 2007 528 541
43. S.C. Hsu, and C.-F. Chien Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing Int J Prod Econ 107 1 2007 88 103
44. C.-F. Chien, and C.Y. Hsu Data mining for optimizing IC feature designs to enhance overall wafer effectiveness IEEE Trans Semicond Manuf 27 1 2014 71 82
45. C.-F. Chien, H.K. Chen, J.Z. Wu, and H.K. C.H. Construct the OGE for promoting tool group productivity in semiconductor manufacturing Int J Prod Res 45 3 2007 509 524
46. C.-F. Chien, C.Y. Hsu, and K.H. Chang Overall wafer effectiveness (OWE): a novel industry standard for semiconductor ecosystem as a whole Comput Indust Eng 65 1 2013 117 127
47. C.-F. Chien, S. Dauzere-Peres, H. Ehm, J.W. Fowler, Z. Jiang, S. Krishnaswamy, T. Lee, L. Moench, and R. Uzsoy Modeling and analysis of semiconductor manufacturing in a shrinking world: challenges and successes Eur J Ind Eng 5 3 2011 254 271