Improvements in polysilicon etch bias and transistor gate control with module level APC methodologies

IEEE Transactions on Semiconductor Manufacturing

Volumn 18, Issue 4, 2005, Pages 522-527

  Williams, David A ^a   Locander, Aaron R ^a,b   Herrera, Ted ^a   Garza, John D ^a   Parker, Cynthia K ^a,c  

^a INTEL CORPORATION   (United States)

^b Intel ^*

^c Lithography Capital Equipment Development   (United States)

Author keywords

Etching; Lithography; Process control; Semiconductor device manufacture

Indexed keywords

CRITICAL DIMENSIONS (CD); DEVICE PERFORMANCE; ELECTRICAL GATE DIMENSION;

LITHOGRAPHY; PERSONNEL; POLYSILICON;

GATES (TRANSISTOR);

EID: 28644449679     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2005.858490     Document Type: Conference Paper

References (7)

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