-
1
-
-
0000273410
-
Capital productivity: Major challenge for the semiconductor industry
-
P. Silverman, "Capital productivity: Major challenge for the semiconductor industry," Solid State Technol., vol. 37, no. 3, p. 104, 1994.
-
(1994)
Solid State Technol.
, vol.37
, Issue.3
, pp. 104
-
-
Silverman, P.1
-
2
-
-
0000793139
-
Cramming more components onto integrated circuits
-
G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, pp. 114-117, 1965.
-
(1965)
Electronics
, vol.38
, Issue.8
, pp. 114-117
-
-
Moore, G.E.1
-
3
-
-
78049265768
-
Manufacturing intelligence for semiconductor demand forecast based on technology diffusion and product life cycle
-
C.-F. Chien, Y.-J. Chen, and J.-T. Peng, "Manufacturing intelligence for semiconductor demand forecast based on technology diffusion and product life cycle," Int. J. Prod. Econ., vol. 128, no. 2, pp. 496-509, 2010.
-
(2010)
Int. J. Prod. Econ.
, vol.128
, Issue.2
, pp. 496-509
-
-
Chien, C.-F.1
Chen, Y.-J.2
Peng, J.-T.3
-
4
-
-
78651071873
-
Manufacturing intelligence to exploit the value of production and tool data to reduce cycle time
-
Jan
-
C.-J. Kuo, C.-F. Chien, and J. Chen, "Manufacturing intelligence to exploit the value of production and tool data to reduce cycle time," IEEE Trans. Autom. Sci. Eng., vol. 8, no. 1, pp. 103-111, Jan. 2011.
-
(2011)
IEEE Trans. Autom. Sci. Eng.
, vol.8
, Issue.1
, pp. 103-111
-
-
Kuo, C.-J.1
Chien, C.-F.2
Chen, J.3
-
5
-
-
84870865605
-
Manufacturing intelligence to forecast and reduce semiconductor cycle time
-
C.-F. Chien, C.-Y. Hsu, and C.-W. Hsiao, "Manufacturing intelligence to forecast and reduce semiconductor cycle time," J. Intell. Manuf., vol. 23, no. 6, pp. 2281-2294, 2012.
-
(2012)
J. Intell. Manuf.
, vol.23
, Issue.6
, pp. 2281-2294
-
-
Chien, C.-F.1
Hsu, C.-Y.2
Hsiao, C.-W.3
-
6
-
-
84874614565
-
A system for online detection and classification of wafer bin map defect patterns for manufacturing intelligence
-
C.-F. Chien, S.-C. Hsu, and Y.-J. Chen, "A system for online detection and classification of wafer bin map defect patterns for manufacturing intelligence," Int. J. Prod. Res., vol. 51, no. 8, pp. 2324-2338, 2013.
-
(2013)
Int. J. Prod. Res.
, vol.51
, Issue.8
, pp. 2324-2338
-
-
Chien, C.-F.1
Hsu, S.-C.2
Chen, Y.-J.3
-
8
-
-
84879695405
-
Overall wafer effectiveness (OWE): A novel industry standard for semiconductor ecosystem as a whole
-
C.-F. Chien, C.-Y. Hsu, and K.-H. Chang, "Overall wafer effectiveness (OWE): A novel industry standard for semiconductor ecosystem as a whole," Comput. Ind. Eng., vol. 65, no. 1, pp. 117-127, 2013.
-
(2013)
Comput. Ind. Eng.
, vol.65
, Issue.1
, pp. 117-127
-
-
Chien, C.-F.1
Hsu, C.-Y.2
Chang, K.-H.3
-
9
-
-
0033326954
-
Iterative cutting procedure for determining the optimal wafer exposure pattern
-
DOI 10.1109/66.778206
-
C.-F. Chien, S.-C. Hsu, and C. Chen, "An iterative cutting procedure for determining the optimal wafer exposure pattern," IEEE Trans. Semicond. Manuf., vol. 12, no. 3, pp. 375-377, Aug. 1999. (Pubitemid 30507669)
-
(1999)
IEEE Transactions on Semiconductor Manufacturing
, vol.12
, Issue.3
, pp. 375-377
-
-
Chien, C.-F.1
Hsu, S.-C.2
Chen, C.-P.3
-
10
-
-
0035333336
-
A cutting algorithm for optimizing the wafer exposure pattern
-
DOI 10.1109/66.920727, PII S0894650701035199
-
C.-F. Chien, S. Hsu, and J. Deng, "A cutting algorithm for optimizing the wafer exposure pattern," IEEE Trans. Semicond. Manuf., vol. 14, no. 2, pp. 157-162, May 2001. (Pubitemid 32495616)
-
(2001)
IEEE Transactions on Semiconductor Manufacturing
, vol.14
, Issue.2
, pp. 157-162
-
-
Chien, C.-F.1
Hsu, S.-C.2
Deng, J.-F.3
-
11
-
-
84879694233
-
-
U.S. Patent 735307 7B2, Apr. 1
-
C.-W. Lin, H.-H. Chou, Y.-J. Wang, C.-F. Chien, J.-H. Wang, and C.-H. Hsiao, "Methods for optimizing die placement," U.S. Patent 735 307 7B2, Apr. 1, 2008.
-
(2008)
Methods for Optimizing Die Placement
-
-
Lin, C.-W.1
Chou, H.-H.2
Wang, Y.-J.3
Chien, C.-F.4
Wang, J.-H.5
Hsiao, C.-H.6
-
12
-
-
84894046016
-
-
U.S. Patent Application Publication 201 201 626 22A1, Jun. 28
-
A. Varela, M. A. Maxim, D. E. Vanlare, and A. Lazar. "Field extension to reduce non-yeilding exposures of wafer," U.S. Patent Application Publication 201 201 626 22A1, Jun. 28, 2012.
-
(2012)
Field extension to reduce non-yeilding exposures of wafer
-
-
Varela, A.1
Maxim, M.A.2
Vanlare, D.E.3
Lazar, A.4
-
13
-
-
0024480972
-
An algebraic expression to count the number of chips on a wafer
-
Jan
-
A. Ferris-Prabhu, "An algebraic expression to count the number of chips on a wafer," IEEE Circuits Devices Mag., vol. 5, no. 1, pp. 37-39, Jan. 1989.
-
(1989)
IEEE Circuits Devices Mag.
, vol.5
, Issue.1
, pp. 37-39
-
-
Ferris-Prabhu, A.1
-
14
-
-
13844256345
-
Investigation of gross die per wafer formulas
-
DOI 10.1109/TSM.2004.836656
-
D. K. de Vries, "Investigation of gross die per wafer formulas," IEEE Trans. Semicond. Manuf., vol. 18, no. 1, pp. 136-139, Feb. 2005. (Pubitemid 40245407)
-
(2005)
IEEE Transactions on Semiconductor Manufacturing
, vol.18
, Issue.1
, pp. 136-139
-
-
De Vries, D.K.1
-
15
-
-
0033284013
-
The economics of yield-driven processes
-
R. E. Bohn and C. Terwiesch, "The economics of yield-driven processes," J. Oper. Manag., vol. 18, no. 1, pp. 41-59, 1999.
-
(1999)
J. Oper. Manag.
, vol.18
, Issue.1
, pp. 41-59
-
-
Bohn, R.E.1
Terwiesch, C.2
-
16
-
-
0026417870
-
Designing an optimal production system with inspection
-
C. S. Tang, "Designing an optimal production system with inspection," Eur. J. Operat. Res., vol. 52, no. 1, pp. 45-54, 1991.
-
(1991)
Eur. J. Operat. Res.
, vol.52
, Issue.1
, pp. 45-54
-
-
Tang, C.S.1
-
17
-
-
0033716420
-
Behind the learning curve: Linking learning activities to waste reduction
-
M. A. Lapré, A. S. Mukherjee, and L. N. Van Wassenhove, "Behind the learning curve: Linking learning activities to waste reduction," Manag. Sci., vol. 46, no. 5, pp. 597-611, 2000.
-
(2000)
Manag. Sci.
, vol.46
, Issue.5
, pp. 597-611
-
-
Lapré, M.A.1
Mukherjee, A.S.2
Van Wassenhove, L.N.3
-
18
-
-
0029207742
-
Noise and learning in semiconductor manufacturing
-
R. E. Bohn, "Noise and learning in semiconductor manufacturing," Manag. Sci., vol. 41, no. 1, pp. 31-42, 1995.
-
(1995)
Manag. Sci.
, vol.41
, Issue.1
, pp. 31-42
-
-
Bohn, R.E.1
-
19
-
-
33751531825
-
Mask cost and profitability in photomask manufacturing: An empirical analysis
-
DOI 10.1109/TSM.2006.883577
-
C. M. Weber, C. N. Berglund, and P. Gabella, "Mask cost and profitability in photomask manufacturing: An empirical analysis," IEEE Trans. Semicond. Manuf., vol. 19, no. 4, pp. 465-474, Nov. 2006. (Pubitemid 44832950)
-
(2006)
IEEE Transactions on Semiconductor Manufacturing
, vol.19
, Issue.4
, pp. 465-474
-
-
Weber, C.M.1
Berglund, C.N.2
Gabella, P.3
-
20
-
-
35348898603
-
Economie efficiency analysis of wafer fabrication
-
DOI 10.1109/TASE.2007.906142
-
R. C. Leachman, S. Ding, and C.-F. Chien, "Economic effciency analysis of wafer fabrication," IEEE Trans. Autom. Sci. Eng., vol. 4, no. 4, pp. 501-512, Oct. 2007. (Pubitemid 47573845)
-
(2007)
IEEE Transactions on Automation Science and Engineering
, vol.4
, Issue.4
, pp. 501-512
-
-
Leachman, R.C.1
Ding, S.2
Chien, C.-F.3
-
21
-
-
76849097608
-
Scale, scope, and speed-managing the challenges of multiproduct manufacturing
-
Feb
-
C. M. Weber and A. Fayed, "Scale, scope, and speed-managing the challenges of multiproduct manufacturing," IEEE Trans. Semicond. Manuf., vol. 23, no. 1, pp. 30-38, Feb. 2010.
-
(2010)
IEEE Trans. Semicond. Manuf.
, vol.23
, Issue.1
, pp. 30-38
-
-
Weber, C.M.1
Fayed, A.2
-
22
-
-
0035283518
-
Learning and process improvement during production ramp-up
-
DOI 10.1016/S0925-5273(00)00045-1
-
C. Terwiesch and R. E. Bohn, "Learning and process improvement during production ramp-up," Int. J. Prod. Econ., vol. 70, no. 1, pp. 1-19, 2001. (Pubitemid 32160564)
-
(2001)
International Journal of Production Economics
, vol.70
, Issue.1
, pp. 1-19
-
-
Terwiesch, C.1
Bohn, R.E.2
-
23
-
-
33846902258
-
Integration of speed economics into decision-making for manufacturing management
-
DOI 10.1016/j.ijpe.2006.08.012, PII S0925527306002398, Building Core-Competence Through Operational Excellence
-
R. C. Leachman and S. Ding, "Integration of speed economics into decision-making for manufacturing management," Int. J. Prod. Econ., vol. 107, no. 1, pp. 39-55, 2007. (Pubitemid 46241854)
-
(2007)
International Journal of Production Economics
, vol.107
, Issue.1
, pp. 39-55
-
-
Leachman, R.C.1
Ding, S.2
-
24
-
-
9144249190
-
Yield learning and the sources of profitability in semiconductor manufacturing and process development
-
Nov
-
C. Weber, "Yield learning and the sources of profitability in semiconductor manufacturing and process development," IEEE Trans. Semicond. Manuf., vol. 17, no. 4, pp. 590-596, Nov. 2004.
-
(2004)
IEEE Trans. Semicond. Manuf.
, vol.17
, Issue.4
, pp. 590-596
-
-
Weber, C.1
-
25
-
-
0029304803
-
Semiconductor yield improvement: Results and best practices
-
May
-
S. P. Cunningham, C. J. Spanos, and K. Voros, "Semiconductor yield improvement: Results and best practices," IEEE Trans. Semicond. Manuf., vol. 8, no. 2, pp. 103-109, May 1995.
-
(1995)
IEEE Trans. Semicond. Manuf.
, vol.8
, Issue.2
, pp. 103-109
-
-
Cunningham, S.P.1
Spanos, C.J.2
Voros, K.3
-
26
-
-
0036474654
-
Data mining for improving a cleaning process in the semiconductor industry
-
DOI 10.1109/66.983448, PII S0894650702010278
-
D. Braha and A. Shmilovici, "Data mining for improving a cleaning process in the semiconductor industry," IEEE Trans. Semicond. Manuf., vol. 15, no. 1, pp. 91-101, Feb. 2002. (Pubitemid 34278389)
-
(2002)
IEEE Transactions on Semiconductor Manufacturing
, vol.15
, Issue.1
, pp. 91-101
-
-
Braha, D.1
Shmilovici, A.2
-
27
-
-
33845660695
-
Data mining for yield enhancement in semiconductor manufacturing and an empirical study
-
DOI 10.1016/j.eswa.2006.04.014, PII S095741740600131X
-
C.-F. Chien, W.-J. Wang, and J. C. Cheng, "Data mining for yield enhancement in semiconductor manufacturing and an empirical study," Expert Syst. Appl., vol. 33, no. 1, pp. 192-198, 2007. (Pubitemid 44959928)
-
(2007)
Expert Systems with Applications
, vol.33
, Issue.1
, pp. 192-198
-
-
Chien, C.-F.1
Wang, W.-C.2
Cheng, J.-C.3
-
29
-
-
0003802343
-
-
Belmont CA USA: Wadsworth
-
L. Breiman, J. H. Friedman, R. J. Olshen, and C. J. Stone, Classification and Regression Trees. Belmont, CA, USA: Wadsworth, 1984.
-
(1984)
Classification and Regression Trees
-
-
Breiman, L.1
Friedman, J.H.2
Olshen, R.J.3
Stone, C.J.4
-
30
-
-
0037565156
-
Model trees as an alternative to neural networks in rainfall-runoff modelling
-
D. P. Solomatine and K. N. Dulal, "Model trees as an alternative to neural networks in rainfall-runoff modelling," J. Sci. Hydrol., vol. 48, no. 3, pp. 399-411, 2003.
-
(2003)
J. Sci. Hydrol.
, vol.48
, Issue.3
, pp. 399-411
-
-
Solomatine, D.P.1
Dulal, K.N.2
-
31
-
-
12144264770
-
Neural networks and M5 model trees in modelling water level-discharge relationship
-
DOI 10.1016/j.neucom.2004.04.016, PII S0925231204003315
-
B. Bhattacharya and D. P. Solomatine, "Neural networks and M5 model trees in modelling water level-discharge relationship," Neurocomputing, vol. 63, pp. 381-396, Jan. 2005. (Pubitemid 40103871)
-
(2005)
Neurocomputing
, vol.63
, Issue.SPEC. ISSUE.
, pp. 381-396
-
-
Bhattacharya, B.1
Solomatine, D.P.2
-
32
-
-
71549124103
-
Comparison between M5 model tree and neural networks for prediction of significant wave height in lake superior
-
A. Etemad-Shahidi and J. Mahjoobi, "Comparison between M5 model tree and neural networks for prediction of significant wave height in lake superior," Ocean Eng., vol. 36, nos. 15-16, pp. 1175-1181, 2009.
-
(2009)
Ocean Eng.
, vol.36
, Issue.15-16
, pp. 1175-1181
-
-
Etemad-Shahidi, A.1
Mahjoobi, J.2
-
35
-
-
84894080993
-
-
Harvard Business School, Boston, MA, USA, Tech. Rep. HBS Case 9-608-159
-
W. Shih, C. Shih, C.-F. Chien, and Y. Chang, "System on a chip 2008: Global Unichip Corporation," Harvard Business School, Boston, MA, USA, Tech. Rep. HBS Case 9-608-159, 2008.
-
(2008)
System on A Chip 2008: Global Unichip Corporation
-
-
Shih, W.1
Shih, C.2
Chien, C.-F.3
Chang, Y.4
-
36
-
-
50249108393
-
Economic analysis of 450mm wafer migration
-
C.-F. Chien, J.-K. Wang, T.-C. Chang, and W.-C. Wu, "Economic analysis of 450mm wafer migration," in Proc. ISSM, 2007, pp. 283-286.
-
(2007)
Proc. ISSM
, pp. 283-286
-
-
Chien, C.-F.1
Wang, J.-K.2
Chang, T.-C.3
Wu, W.-C.4
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