Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2014, Pages 440-451

  Ansari, Amin ^a   Mishra, Asit ^b,c   Xu, Jianping ^b   Torrellas, Josep ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b INTEL CORPORATION   (United States)

^c QUALCOMM INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ENERGY EFFICIENCY; ENERGY UTILIZATION; ERRORS; SUPERCOMPUTERS;

DYNAMIC VOLTAGE; ENERGY EFFICIENT; FUTURE NETWORKS; NETWORK ENERGY CONSUMPTION; NETWORK FREQUENCY; ON-CHIP NETWORKS; PERFORMANCE IMPACT; WITHIN-DIE PARAMETER VARIATIONS;

ROUTERS;

EID: 84903977448     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2014.6835953     Document Type: Conference Paper

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