A case for dynamic frequency tuning in on-chip networks

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 292-303

  Mishra, Asit K ^a   Das, Reetuparna ^a   Eachempati, Soumya ^a   Iyer, Ravi ^b   Vijaykrishnan, N ^a   Das, Chita R ^a  

^a The Pennsylvania State University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

C.1.2 multiprocessors : interconnection architectures; C.1.4 parallel architectures : distributed architectures; Design; Experimentation; Performance

Indexed keywords

C.1.2 [MULTIPROCESSORS]: INTERCONNECTION ARCHITECTURES; DE FACTO STANDARD; DISTRIBUTED ARCHITECTURE; DYNAMIC FREQUENCY; DYNAMIC VOLTAGE AND FREQUENCY SCALING; ENERGY DELAY PRODUCT; FIRST ORDER DESIGN; HIGH LOAD; INTERCONNECTION ARCHITECTURE; NETWORK LOAD; NETWORK-ON-CHIPS; ON-CHIP NETWORKS; POWER CONSUMPTION; POWER MANAGEMENTS; POWER SAVINGS; ROUTER ARCHITECTURE; ROUTER PIPELINE; SCALABLE COMMUNICATION; SYNTHETIC WORKLOADS;

BENCHMARKING; BIOLOGICAL MATERIALS; DESIGN; ENERGY MANAGEMENT; EXPERIMENTS; MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; PARALLEL ARCHITECTURES; TUNING;

ROUTERS;

EID: 76749088475     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669151     Document Type: Conference Paper

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