VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2012, Pages

  Karpuzcu, Ulya R ^a   Kolluru, Krishna B ^b   Kim, Nam Sung ^b   Torrellas, Josep ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

Manycore architectures; Near threshold voltage; Power constraints; Process variations; SRAM fault models

Indexed keywords

ENERGY EFFICIENT; FAULT MODEL; FAULT RATES; HIGHER FREQUENCIES; LOWER FREQUENCIES; MANY-CORE; MANY-CORE ARCHITECTURE; ON CHIPS; POWER CONSTRAINTS; POWER VARIATIONS; PROCESS VARIATION; SRAM CELL; SUPPLY VOLTAGES; VARIATION MODELS;

NETWORK ARCHITECTURE; THRESHOLD VOLTAGE;

SENSITIVITY ANALYSIS;

EID: 84866660547     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2012.6263951     Document Type: Conference Paper

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