VARIUS: A model of process variation and resulting timing errors for microarchitects

IEEE Transactions on Semiconductor Manufacturing

Volumn 21, Issue 1, 2008, Pages 3-13

  Sarangi, Smruti R ^b   Greskamp, Brian ^a,c   Teodorescu, Radu ^a,c   Nakano, Jun ^a,d   Tiwari, Abhishek ^a,c   Torrellas, Josep ^a,c  

^a IEEE

^b Synopsis Research   (India)

^c University of Illinois at Urbana Champaign   (United States)

^d IBM JAPAN LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION; PROBLEM SOLVING; RANDOM PROCESSES; STATISTICS;

LEAKAGE POWER; MICROARCHITECTS; MICROPROCESSOR DESIGN; PROCESS PARAMETERS;

ERROR ANALYSIS;

EID: 38949186007     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2007.913186     Document Type: Conference Paper

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