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Volumn 34, Issue 4, 2001, Pages 52-58

Power: A first-class architectural design constraint

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CONSTRAINT THEORY; ELECTRIC POWER UTILIZATION; INFORMATION TECHNOLOGY; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; POWER ELECTRONICS; SEMICONDUCTOR STORAGE;

EID: 0035311079     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.917539     Document Type: Article
Times cited : (360)

References (12)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.