Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability

IEEE Micro

Volumn 28, Issue 1, 2008, Pages 60-68

  Liang, Xiaoyao ^a   Canal, Ramon ^b   Wei, Gu Yeon ^a   Brooks, David ^a  

^a HARVARD UNIVERSITY   (United States)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Caches; Dynamic memory; Process variation; Variability

Indexed keywords

COMPUTER ARCHITECTURE; DYNAMIC RANDOM ACCESS STORAGE; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE;

DYNAMIC MEMORY; PROCESS VARIATION;

CACHE MEMORY;

EID: 41349100757     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2008.12     Document Type: Article

References (5)

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3. S. Ozdemir et al., "Yield-Aware Cache Architectures," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 06), IEEE CS Press, 2006, pp. 15-25.
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