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Volumn , Issue , 2009, Pages 213-224

BlueShift: Designing processors for timing speculation from the ground up

Author keywords

[No Author keywords available]

Indexed keywords

BLUE SHIFT; COMPUTER ARCHITECTURE; LOGIC DEVICES; TIMING CIRCUITS; VOLTAGE SCALING;

EID: 64949118635     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798256     Document Type: Conference Paper
Times cited : (77)

References (27)
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    • Austin, T.1
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    • 13644260163 scopus 로고    scopus 로고
    • Constructive timing violation for improving energy efficiency
    • Kluwer Academic Publishers
    • T. Sato and I. Arita. Constructive timing violation for improving energy efficiency. Compilers and operating systems for low power. Kluwer Academic Publishers, 2003.
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    • Sato, T.1    Arita, I.2
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    • 0036056699 scopus 로고    scopus 로고
    • G. Sery, S. Borkar, and V. De. Life is CMOS: Why chase the life after. In Design Automation Conference, June 2002.
    • G. Sery, S. Borkar, and V. De. Life is CMOS: Why chase the life after. In Design Automation Conference, June 2002.
  • 19
    • 84868915181 scopus 로고    scopus 로고
    • Sun Microsystems. OpenSPARC T1 RTL release 1.5
    • Sun Microsystems. OpenSPARC T1 RTL release 1.5. http://www.opensparc.net/ opensparc-t1/index.html.
  • 21
    • 64949144555 scopus 로고    scopus 로고
    • S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. Jouppi. CACTI 5.1. Technical Report HPL-2008-20, Hewlett Packard Labs, April 2008.
    • S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. Jouppi. CACTI 5.1. Technical Report HPL-2008-20, Hewlett Packard Labs, April 2008.
  • 22
    • 0036858210 scopus 로고    scopus 로고
    • Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
    • November
    • J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE Journal of Solid State Circuits, 37(11), November 2002.
    • (2002) IEEE Journal of Solid State Circuits , vol.37 , Issue.11
    • Tschanz, J.1    Kao, J.2    Narendra, S.3    Nair, R.4    Antoniadis, D.5    Chandrakasan, A.6    De, V.7
  • 23
    • 64949142647 scopus 로고    scopus 로고
    • A 130nm generation logic technology featuring 70nm transistors, dual Vt transistors and 6 layers of Cu interconnects
    • December
    • S. Tyagi et al. A 130nm generation logic technology featuring 70nm transistors, dual Vt transistors and 6 layers of Cu interconnects. In IEEE Electron Devices Meeting, December 2000.
    • (2000) IEEE Electron Devices Meeting
    • Tyagi, S.1
  • 24
    • 24544451157 scopus 로고    scopus 로고
    • Achieving typical delays in synchronous systems via timing error toleration
    • Technical Report 032000-0100, University of Rhode Island Department of Electrical and Computer Engineering, March
    • A. Uht. Achieving typical delays in synchronous systems via timing error toleration. Technical Report 032000-0100, University of Rhode Island Department of Electrical and Computer Engineering, March 2000.
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    • HotLeakage: A temperature-aware model of subthreshold and gate leakage for architects
    • Technical Report CS-2003-05, University of Virginia, March
    • Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan. HotLeakage: A temperature-aware model of subthreshold and gate leakage for architects. Technical Report CS-2003-05, University of Virginia, March 2003.
    • (2003)
    • Zhang, Y.1    Parikh, D.2    Sankaranarayanan, K.3    Skadron, K.4    Stan, M.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.