Impact of process and temperature variations on network-on-chip design exploration

Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008

Volumn , Issue , 2008, Pages 117-126

  Li, Bin ^a   Peh, Li Shiuan ^a   Patra, Priyadarsan ^b  

^a PRINCETON UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK-ON-CHIPS(NOC);

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; TEMPERATURE DISTRIBUTION;

MICROPROCESSOR CHIPS;

EID: 44149117532     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2008.4492731     Document Type: Conference Paper

References (37)

1. J. Tschanz, et al., "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," IEEE Journal of Solid-State Circuits, vol. 37, no. 11. pp. 1396-1402, Nov 2002.
2. A. Keshavarzi, et al., "Effectiveness of reverse body bias for leakage control in scaled dual vt CMOS ICs," in Proc. of the International Symposium on Low Power Electronics and Design, 2001, pp. 207-212.
3. P. Friedberg, et al., "Modeling within-die spatial correlation effects for process-design co-optimization,"in Sixth International Symposium on Quality of Electronic Design ISQED2005, March 2005, pp. 516-521.
4. B. Stine, D. Boning, and J. Chung, "Analysis and decomposition of spatial variation in integrated circuit processes and devices,"IEEE Transactions on Semiconductor Manufacturing, vol. 10, pp. 24-41, Feb. 1997.
5. H. Chang and S. S. Sapatnekar, "Full-Chip analysis of leakage power under process variations, including spatial correlations," in Proceedings. 42nd Design Automation Conference, June 2005, pp. 523-528.
6. A. Srivastava, et al., "Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance," in ACM/IEEE Design Automation Conference, June 2005, pp. 535-540.
7. S. Zhang, V. Wason, and K. Banerjee, "A probabilistic framework to estimate full-chip subthreshold leakage power distribution considering within-die and die-to-die P-V-T variations," in Proceedings of the 2004 International Symposium on Low Power Electronics and Design ISLPED'04, 2004, pp. 156-161.
8. R. R. Rao, et al., "Parametric yield estimation considering leakage variability," in ACM/IEEE Design Automation Conference, June 2004, pp. 442-447.
9. S. Mukhopadhyay and K. Roy, "Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation," in Proc. of International Symposium on Low Power Electronics and Design, August 2003, pp. 172-175.
10. S. Narendra, et al., "Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS," in Proc. of International Symposium on Low Power Electronics and Design, August 2002, pp. 19-23.
11. H. Su, et al., "Full chip leakage estimation considering power supply and temperature variations," in Proceedings of the 2003 International Symposium on Low Power Electronics and DesignISLPED'03, August 2003, pp. 78-83.
12. E.Humenay, "Toward an architectural treatment of parameter variations "Univ. of Virginia dept. of computer science, Tech. Rep. CS-2005, 2005.
13. C. Saumya, et al., "Considering process variations during system-Level power analysis," in Proc. of the International Symposium on Low Power Electronics and Design, Oct 2006, pp. 342-345.
14. E. Humenay, D. Tarjan, and K. Skadron, "Impact of parameter variations on multi-core chips," in Proc. Wkshp. on Architecture Support for Gigascale Integration. 2006.
15. D. Marculescu and E. Talpes, "Energy awareness and uncertainty in microarchitecture-level design," IEEE Micro, vol. 25, no. 5, pp. 64-76, Sept.-Oct. 2005.
16. N. Azizi, et al., "Variations-aware low-power design with voltage scaling," in Proceedings. 42nd Design Automation Conference, June 2005, pp. 529-534.
17. W. J. Dally and B. Towles, "Route packets not wires: On-chip interconnection networks "in Proc. Design Automation Conf., June 2001.
18. L. Benini and G. De Micheli, "Networks on chips: A new SoC paradigm," IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
19. th International Symposium on Low Power Electronics and Design (ISLPED'03), August 2003, pp. 424-427.
20. H. Wang, L.-S. Peh, and S. Malik, "Power-driven design of router microarchitectures in on-chip networks," Proceedings. 36th Annual IEEE/ACM International on Microarchitecture MICRO-36, pp. 105-116, Dec. 2003.
21. 2 Router for Network-on-Chip Applications," in 2007 IEEE Symposium on VLSI Circuits, 2007.
22. V. Soteriou, et al., "Polaris: A System-Level roadmapping toolchain for On-Chip interconnection networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 8, pp. 855-868, Aug 2007.
23. S. P. Mohanty, et al., Low-Power High-Level Synthesis for Nanoscale CMOS Circuits, 1 st ed. Springer, ISBN:978-0387764733, April 2008.
24. U. C. Berkeley., "BSIM3v3.1 SPICE MOS device models," http://www-device.EECS.Berkeley.EDU/bsim3/, 1997.
25. "Predictive technology model," www.eas.asu.eduTptm.
26. "Polaris,"http://www.princeton.edu/~eisley/polaris.html.
27. V. Soteriou, H. Wang, and L. Peh, "A statistical traffic model for on-Chip interconnection networks," in 14th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), Monterey, California, September 2006, pp. 104-116.
28. th International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2004.
29. th Int. Symp. High Perf. Comp. Arch., Jan. 2001, pp. 255-266.
30. H.-S. Wang, et al., "Orion: A power-performance simulator for interconnection networks." in Proceedings. 35th Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 2002, pp. 294-305.
31. Semiconductor Industry Association, "International technology roadmap for semiconductors."
32. X.-N. Chen and L.-S. Peh, "Leakage power modeling and optimization of interconnection networks," in Proceedings of the 2003 International Symposium on Low Power Electronics and DesignISLPED'03, Aug. 2003, pp. 90-95.
33. Y. Zhang, et al., "Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects," University of Virginia, Tech. Rep. CS-2003-05, March 2003.
34. J. Butts and G. Sohi, "A static power model for architects," in Proceedings. 33rd Annual IEEE/ACM International Symposium on Microarchitecture MICRO-33, 2000, pp. 191-201.
35. Y. Yang, et al., "Adaptive chip-package thermal analysis for synthesis and design,"in Proc. of IEEE Conf. on Design, Automation, and Test in Europe (DATE'06), March 2006. pp. 1-6.
36. S. Vangal, et al., "An 80-Tile 1.28TFLOPS Network-onChip in 65nm CMOS,"in IEEE International Solid-State Circuits Conference ISSCC2007, Feb. 2007, pp. 98-589.
37. S. P. Mohanty, et al., "Interdependency Study of Process and Design Parameter Scaling for Power Optimization of Nano-CMOS Circuits under Process Variation," in Proceedings of the 16th ACM/IEEE International Workshop on Logic and Synthesis (IWLS), 2007. pp. 207-213.