A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS

2007 IEEE International Conference on Computer Design, ICCD 2007

Volumn , Issue , 2007, Pages 63-70

  Kumar, Amit ^a   Kundu, Partha ^b   Singh, Arvind P ^c   Peh, Li Shiuan ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

^b INTEL CORPORATION   (United States)

^c INTEL TECHNOLOGY INDIA PVT LTD   (India)

Author keywords

[No Author keywords available]

Indexed keywords

65NM TECHNOLOGY; ALLOCATION MECHANISMS; ALLOCATOR; CHIP MULTI PROCESSORS; CLOCK FREQUENCIES; COMPUTER DESIGNS; CRITICAL PATH DELAYS; DESIGN CHALLENGES; DESIGN CONSTRAINTS; DETAILED DESIGN; HIGH THROUGHPUTS; HIGH-BANDWIDTH COMMUNICATION; INTERNATIONAL CONFERENCES; LOW-COMPLEXITY; LOW-LATENCY; ON-CHIP NETWORK; ON-CHIP NETWORKS; PRE-FETCHING; ROUTER PIPELINE; SCALE-UP; SHARED BUFFERS; SHARED MEMORIES; VIRTUAL CHANNELS;

CHLORINE COMPOUNDS; ELECTRIC NETWORK TOPOLOGY; ELECTRON BEAM LITHOGRAPHY; EMBEDDED SYSTEMS; FREQUENCY ALLOCATION; MACHINE DESIGN; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; PIPELINES; TECHNOLOGY; THROUGHPUT;

ROUTERS;

EID: 52949114554     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2007.4601881     Document Type: Conference Paper

References (20)

1. T. E. Anderson et al. High speed switch scheduling for local area networks. ACM Trans. Computer Systems, 11(4):319-352, Nov. 1993.
2. P. Bai et al. A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 SRAM cell. In Proc. Int. Electronic Devices Meeting, pages 657-660, Dec. 2004.
3. L. Benini and G. D. Micheli. Networks on chips: A new SoC paradigm. IEEE Computer, 35(1):70-78, Jan. 2002.
4. S. Borkur. Performance, power and the platform. Technology @ Intel Magazine, Nov. 2005.
5. W. J. Dally and B. Towles. Route packets not wires: On-chip interconnection networks. In Proc. Design Automation Conf., pages 684-689, June 2001.
6. W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, 2004.
7. M. Gulles. Scalable pipelined interconnect for distributed endpoint routing: The SGI SPIDER chip. In Proc. Hot Interconnects 4, pages 141-146, Aug. 1996.
8. P. Gratz et al. Implementation and evaluation of a dynamically routed processor operand network. In Proc. Int. Symp. Networks-on-Chip, pages 7-17, May 2007.
9. C. Hughes et al. Physical simulation for animation and visual effects: Parallelization and characterization for chip multiprocessors. In Proc. Int. Symp. Computer Architecture, June 2007.
10. A. Jalabert et al. XpipesCompiler: A tool for instantiating application specific networks-on-chip. In Proc. Design Automation and Test in Europe Conf., Feb. 2004.
11. N. E. Jerger, M. Lipasti, and L.-S. Peh. Circuit-switched coherence. Computer Architecture Letters, 6(1 ):5-8, Jan. 2007.
12. K. Lee, S.-J. Lee, and H. J. Yoo. Low power network-on-chip for high performance SoC design. IEEE Trans. VLSI Systems, 14(2): 148-160, Feb. 2006.
13. S.S. Mukherjee et al. A comparative study of arbitration algorithms for the Alpha 21364 pipelined router. In Proc. Int. Conf. Architectural Support for Programming Languages and Operating Systems, pages 223-234. Oct. 2002.
14. R. Mullins, A. West, and S. Moore. The design and implementation of a low-latency on-chip network. In Proc. Asia and South Pacific-Design Automation Conf., pages 164-169, Jan. 2006.
15. L.-S. Peh and W. J. Dally. A delay model and speculative architecture for pipelined routers. In Proc. Int. Symp. High Performance Computer Architecture, pages 255-266, Jan. 2001.
16. A. Pullini et al. NoC design and implementation in 65nm technology. In Proc. Int. Symp. Networks-on-Chip, May 2007.
17. Y. Tamir and G. L. Frazier. Dynamically-allocated multi-queue buffers for VLSI communication switches. IEEE Trans. Computers, 41(6):725-737, June 1992.
18. S. Tota, M. R. Casu, and L. Maccahiarulo. Implementation analysis of NoC: A MPSoC trace-driven approach. In Proc. ACM Great Lakes Symp. on VLSI, pages 204-209, 2006.
19. S. Vangal, N. Borkar. and A. Alvandpour. A six-port 57GB/s double-pumped nonblocking router core. In Proc. Symp. VLSI Circuits, pages 268-269, June 2005.
20. S. Vangal et al. An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS. In Proc. Int. Solid-State Circuits Conf., Feb. 2007.