Within-die variation-aware dynamic-voltage-frequency-scaling with optimal core allocation and thread hopping for the 80-core TeraFLOPS processor

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 1, 2011, Pages 184-193

  Dighe, Saurabh ^a   Vangal, Sriram R ^a   Aseron, Paolo ^a   Kumar, Shasi ^b   Jacob, Tiju ^b   Bowman, Keith A ^a   Howard, Jason ^a   Tschanz, James ^a   Erraguntla, Vasantha ^b   Borkar, Nitin ^a   De, Vivek K ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

^b INTEL TECHNOLOGY INDIA PVT LTD   (India)

Author keywords

80 core; Core to core variations; DVFS; dynamic voltage frequency scaling; network on chip (NoC); TeraFLOPS processor; variation aware; within die variations

Indexed keywords

80-CORE; CORE-TO-CORE VARIATIONS; DVFS; DYNAMIC VOLTAGE FREQUENCY SCALING; NETWORK ON CHIP; TERAFLOPS PROCESSOR; VARIATION-AWARE; WITHIN-DIE VARIATIONS;

DIES; MICROPROCESSOR CHIPS; OPTIMIZATION; SERVERS; VLSI CIRCUITS;

ENERGY EFFICIENCY;

EID: 78650896343     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2080550     Document Type: Conference Paper

References (20)

1. S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, C. Roberts, V. Erraguntla, Y. Hoskote, N. Borkar, and S. Borkar, "An 80-tile sub-100WTeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 29-41, Jan. 2008.
2. D. N. Truong, W. H. Cheng, T. Mohsenin, Y. Zhiyi, A. T. Jacobson, G. Landge, M. J. Meeuwsen, C. Watnik, A. T. Tran, X. Zhibin, E. W. Work, J. W. Webb, P. V. Mejia, and B. M. Baas, "A 167-processor computational platform in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1130-1144, Apr. 2009.
3. L. Benini and G. D. Micheli, "Networks on chips: A new SoC paradigm," IEEE Computer, vol. 35, pp. 70-78, Jan. 2002.
4. B. H. Calhoun and A. P. Chandrakasan, "Characterizing and modeling minimum energy operation for subthreshold circuits," in Proc. 2004 IEEE Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2004, pp. 90-95.
5. S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. Das, W. Haensch, E. Nowak, and D. Sylvester, "Ultra-low voltage minimum energy CMOS," IBM J. Res. Devel., vol. 50, no. 4/5, pp. 469-490, 2006.
6. K. Bowman, S. Duvall, and J. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 183-190, Feb. 2002.
7. S. Borkar et al., "Parameter variations and impact on circuits and microarchitecture," in Proc. ACM/IEEE DAC, Jun. 2003, pp. 338-342.
8. J. Li and J. F. Martinez, "Dynamic power-performance adaptation of parallel computation on chip multiprocessors," in Proc. 12th Int. Symp. High-Performance Computer Architecture, 2006, Feb. 11-15, 2006, pp. 77-87.
9. J. Donald and M. Martonosi, "Power efficiency for variation-tolerant multicore processors," in Proc. 2006 IEEE Int. Symp. Low Power Electronics and Design (ISLPED), Oct. 4-6, 2006, pp. 304-309.
10. R. Teodorescu and J. Torrellas, "Variation-aware application scheduling and power management for chip multiprocessors," in Proc. 35th Int. Symp. Computer Architecture, 2008 (ISCA'08), Jun. 21-25, 2008, pp. 363-374.
11. S. Herbert and D. Marculescu, "Variation-aware dynamic voltage/frequency scaling," in Proc. 15th Int. Symp. High-Performance Computer Architecture, 2009 (HPCA), Raleigh, NC, Feb. 2009.
12. S. Vangal, Y. Hoskote, D. Somasekhar, V. Erraguntla, J. Howard, G. Ruhl, V. Veeramachaneni, D. Finan, S. Mathew, and N. Borkar, "A 5 GHz floating point multiply-accumulator in 90 nm dual VT CMOS," in 2003 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2003, vol. 1, pp. 334-497.
13. S. Vangal, A. Singh, J. Howard, S. Dighe, N. Borkar, and A. Alvandpour, "A 5.1 GHz 0.34 mm2 router for network-on-chip applications," in 2007 IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 14-16, 2007, pp. 42-43.
14. T. G. Mattson, R. Van der Wijngaart, and M. Frumkin, "Programming the Intel 80-core network-on-a-chip terascale processor," in Proc. Int. Conf. High Performance Computing, Networking, Storage and Analysis (SC 2008), Nov. 2008, pp. 15-21.
15. J. Tschanz, S. Narendra, Y.Ye, B. Bloechel, S. Borkar, and V. De, "Dynamic sleep transistor and body bias for active leakage power control of microprocessors," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1838-1845, Nov. 2003.
16. A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar, and V. De, "Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs," in Proc. 2001 Int. Symp. Low Power Electronics and Design (ISLPED), Huntington Beach, CA, Aug. 2001, pp. 207-212.
17. P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S.-H. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, and M. Bohr, "A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μmμ SRAM cell," in IEDM Tech. Dig., Dec. 2004, pp. 657-660.
18. B. Zhai, R. Dreslinski, D. Blaauw, T.Mudge, and D. Sylvester, "Energy efficient near threshold chip multiprocessing," in Proc. 2007 Int. Symp. Low-Power Electronics and Design (ISLPED).
19. J. Held, J. Bautista, and S. Koehl, "From a Few Cores to Many: A Tera-Scale Computing Research Overview," white paper, Intel Corp. [Online]. Available: http://download.intel.com/research/platform/ terascale/terascale- overview-paper.pdf
20. K. Kuhn, "Variation in 45 nm and implications for 32 nm and beyond," in 2nd Int. CMOS Variability Conf. 2009, May 2009.