Revival: A variation-tolerant architecture using voltage interpolation and variable latency

IEEE Micro

Volumn 29, Issue 1, 2009, Pages 127-137

  Liang, Xiaoyao ^a   Wei, Gu Yeon ^a   Brooks, David ^a  

^a HARVARD UNIVERSITY   (United States)

Author keywords

Clocks; Delay; Interpolation; Latches; Microarchitecture; Pipelines; Process variations; Tuning; Variable latency; Voltage interpolation

Indexed keywords

NANOTECHNOLOGY; PIPELINES; TUNING;

DELAY; LATCHES; MICROARCHITECTURE; PROCESS VARIATIONS; VARIABLE LATENCY; VOLTAGE INTERPOLATION;

INTERPOLATION;

EID: 63149170541     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2009.13     Document Type: Conference Paper

References (10)

1. K. Bowman, S. Duvall, and J. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration," J. Solid-State Circuits, vol. 37, no. 2, Feb. 2002, pp. 183-190.
2. X. Liang and D. Brooks, "Mitigating the Impact of Process Variations on Processor Register Files and Execution Units," Proc. 39th IEEE Int'l Symp. Microarchitecture (Micro 06), IEEE CS Press, 2006, pp. 504-514.
3. S. Ozdemir et al., "Yield-Aware Cache Architectures," Proc. 39th IEEE/ACM Int'l Symp. Microarchitecture (Micro 06), IEEE CS Press, 2006, pp. 15-25.
4. A. Tiwari, S.R. Sarangi, and J. Torrellas, "Recycle: Pipeline Adaptation to Tolerate Process Variation," Proc. Int'l Symp. Computer Architecture (ISCA 07), ACM Press, 2007, pp. 323-334.
5. R. Teodorescu et al., "Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing," Proc. 40th IEEE Int'l Symp. Microarchitecture (Micro 07), IEEE CS Press, 2007, pp. 27-42.
6. X. Liang, D. Brooks, and G.-Y. Wei, "A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE Press, 2008, pp. 404-405.
7. E. Borch et al., "Loose Loops Sink Chips," Proc. 8th Int'l Symp. High-Performance Computer Architecture (HPCA 02), IEEE CS Press, 2002, pp. 299-310.
8. A.J. Bhavnagarwala, X. Tang, and J.D. Meindl, "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, Apr. 2001, pp. 658-665.
9. A. Agarwal et al., "A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies," IEEE Trans. Very Large Scale Integration Systems, vol. 13, no. 1, Jan. 2005, pp. 27-38.
10. X. Liang, G. Wei, and D. Brooks, "Process Variation Tolerant 3T1D-based Cache Architectures," Proc. 40th IEEE Int'l Symp. Microarchitecture (Micro 07), IEEE CS Press, 2007, pp. 15-26.