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Volumn , Issue , 2010, Pages 55-88

Program and erase of NAND memory arrays

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EID: 84891996352     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-90-481-9431-5_3     Document Type: Chapter
Times cited : (7)

References (66)
  • 1
    • 84944812174 scopus 로고
    • A floating-gate and its application to memory devices
    • D. Kahng and S. Sze, "A floating-gate and its application to memory devices", The Bell System Technical Journal, vol. 46, no. 4, pp. 1288-1295, 1967.
    • (1967) The Bell System Technical Journal , vol.46 , Issue.4 , pp. 1288-1295
    • Kahng, D.1    Sze, S.2
  • 3
    • 33646843945 scopus 로고    scopus 로고
    • Survey on Flash technology with specific attention to the critical process parameters related to manufacturing
    • April
    • G. Ginami et al., "Survey on Flash technology with specific attention to the critical process parameters related to manufacturing", Proceedings of the IEEE, vol. 91, no. 4, pp. 503-522, April 2003.
    • (2003) Proceedings of the IEEE , vol.91 , Issue.4 , pp. 503-522
    • Ginami, G.1
  • 4
    • 0028752012 scopus 로고
    • A 0.67 μm2 self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs
    • Dec.
    • S. Aritome et al., "A 0.67 μm2 self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs", in International Electron Devices Meeting, 1994. IEDM'94. Technical Digest., pp. 61-64, Dec. 1994.
    • (1994) International Electron Devices Meeting, 1994. IEDM'94. Technical Digest. , pp. 61-64
    • Aritome, S.1
  • 6
    • 28044445399 scopus 로고    scopus 로고
    • Scaling down the interpoly dielectric for next generation Flash memory: Challenges and opportunities
    • Nov.
    • B. Govoreanu, D. Brunco, and J. V. Houdt, "Scaling down the interpoly dielectric for next generation Flash memory: Challenges and opportunities", Solid-State Electronics, vol. 49, no. 11, pp. 1841-1848, Nov. 2005.
    • (2005) Solid-state Electronics , vol.49 , Issue.11 , pp. 1841-1848
    • Govoreanu, B.1    Brunco, D.2    Houdt, J.V.3
  • 8
    • 0000090297 scopus 로고    scopus 로고
    • Layered tunnel barriers for nonvolatile memory devices
    • Online
    • K. K. Likharev, "Layered tunnel barriers for nonvolatile memory devices", Applied Physics Letters, vol. 73, no. 15, pp. 2137-2139, 1998. [Online]. Available: http://link.aip.org/link/?APL/73/2137/1
    • (1998) Applied Physics Letters , vol.73 , Issue.15 , pp. 2137-2139
    • Likharev, K.K.1
  • 10
    • 62349114580 scopus 로고    scopus 로고
    • Metal control gate for sub-30nm floating gate NAND memory
    • Nov., 9th Annual
    • N. Chan et al., "Metal control gate for sub-30nm floating gate NAND memory", in Non-Volatile Memory Technology Symposium, 2008. NVMTS 2008. 9th Annual, pp. 1-4, Nov. 2008.
    • (2008) Non-volatile Memory Technology Symposium, 2008. NVMTS 2008 , pp. 1-4
    • Chan, N.1
  • 11
    • 0026107524 scopus 로고
    • ONO inter-poly dielectric scaling for nonvolatile memory applications
    • Feb.
    • S. Mori et al., "ONO inter-poly dielectric scaling for nonvolatile memory applications", IEEE Transactions on Electron Devices, vol. 38, no. 2, pp. 386-391, Feb. 1991.
    • (1991) IEEE Transactions on Electron Devices , vol.38 , Issue.2 , pp. 386-391
    • Mori, S.1
  • 12
    • 46049118849 scopus 로고    scopus 로고
    • Investigation of the low-field leakage through high-k interpoly dielectric stacks and its impact on nonvolatile memory data retention
    • Dec.
    • B. Govoreanu et al., "Investigation of the low-field leakage through high-k interpoly dielectric stacks and its impact on nonvolatile memory data retention", in International Electron Devices Meeting, 2006. IEDM'06, pp. 1-4, Dec. 2006.
    • (2006) International Electron Devices Meeting, 2006. IEDM'06 , pp. 1-4
    • Govoreanu, B.1
  • 14
  • 15
    • 36849097956 scopus 로고
    • Fowler-Nordheim tunneling into thermally grown SiO
    • Online
    • M. Lenzlinger and E. H. Snow, "Fowler-Nordheim tunneling into thermally grown SiO", Journal of Applied Physics, vol. 40, no. 1, pp. 278-283, 1969. [Online]. Available: http://link.aip.org/link/?JAP/40/278/1
    • (1969) Journal of Applied Physics , vol.40 , Issue.1 , pp. 278-283
    • Lenzlinger, M.1    Snow, E.H.2
  • 16
    • 0026897881 scopus 로고
    • Quantum-mechanical modeling of accumulation layers in MOS structure
    • July
    • J. Sune, P. Olivo, and B. Ricco, "Quantum-mechanical modeling of accumulation layers in MOS structure", IEEE Transactions on Electron Devices, vol. 39, no. 7, pp. 1732-1739, July 1992.
    • (1992) IEEE Transactions on Electron Devices , vol.39 , Issue.7 , pp. 1732-1739
    • Sune, J.1    Olivo, P.2    Ricco, B.3
  • 19
    • 0028513959 scopus 로고
    • Correlation of trap generation to charge-to-breakdown (Qbd): A physical-damage model of dielectric breakdown
    • Sept.
    • P. Apte and K. Saraswat, "Correlation of trap generation to charge-to-breakdown (Qbd): a physical-damage model of dielectric breakdown", IEEE Transactions on Electron Devices, vol. 41, no. 9, pp. 1595-1602, Sept 1994.
    • (1994) IEEE Transactions on Electron Devices , vol.41 , Issue.9 , pp. 1595-1602
    • Apte, P.1    Saraswat, K.2
  • 20
    • 68349158939 scopus 로고    scopus 로고
    • Investigation of program saturation in scaled interpoly dielectric floating-gate memory devices
    • Aug.
    • M. F. Beug, N. Chan, T. Hoehr, L. Mueller-Meskamp, and M. Specht, "Investigation of program saturation in scaled interpoly dielectric floating-gate memory devices", IEEE Transactions on Electron Devices, vol. 56, no. 8, pp. 1698-1704, Aug. 2009.
    • (2009) IEEE Transactions on Electron Devices , vol.56 , Issue.8 , pp. 1698-1704
    • Beug, M.F.1    Chan, N.2    Hoehr, T.3    Mueller-Meskamp, L.4    Specht, M.5
  • 21
    • 0028538112 scopus 로고
    • A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND Flash memory
    • Nov.
    • T. Tanaka et al., "A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND Flash memory", IEEE Journal of Solid-State Circuits, vol. 29, no. 11, pp. 1366-1373, Nov. 1994.
    • (1994) IEEE Journal of Solid-state Circuits , vol.29 , Issue.11 , pp. 1366-1373
    • Tanaka, T.1
  • 23
    • 0029404872 scopus 로고
    • A 3.3 V 32 Mb NAND Flash memory with incremental step pulse programming scheme
    • Nov.
    • K.-D. Suh et al., "A 3.3 V 32 Mb NAND Flash memory with incremental step pulse programming scheme", IEEE Journal of Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, Nov. 1995.
    • (1995) IEEE Journal of Solid-state Circuits , vol.30 , Issue.11 , pp. 1149-1156
    • Suh, K.-D.1
  • 24
    • 84886448036 scopus 로고    scopus 로고
    • A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance
    • Dec.
    • S. Satoh et al., "A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance", International Electron Devices Meeting, 1997. IEDM'97. Technical Digest., pp. 291-294, Dec. 1997.
    • (1997) International Electron Devices Meeting, 1997. IEDM'97. Technical Digest. , pp. 291-294
    • Satoh, S.1
  • 25
    • 0031638358 scopus 로고    scopus 로고
    • A novel Channel Boost Capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4 Gbit NAND Flash memories
    • June
    • S. Satoh et al., "A novel Channel Boost Capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4 Gbit NAND Flash memories", in VLSI Technology, 1998. Symposium on Digest of Technical Papers, pp. 108-109, June 1998.
    • (1998) VLSI Technology, 1998. Symposium on Digest of Technical Papers , pp. 108-109
    • Satoh, S.1
  • 27
    • 36448932248 scopus 로고    scopus 로고
    • Bit cost scalable technology with punch and plug process for ultra high density flash memory
    • June
    • H. Tanaka et al., "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory", in IEEE Symposium on VLSI Technology, June 2007, pp. 14-15.
    • (2007) IEEE Symposium on VLSI Technology , pp. 14-15
    • Tanaka, H.1
  • 28
    • 64549122322 scopus 로고    scopus 로고
    • Disturbless Flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device
    • Dec.
    • Y. Komori et al., "Disturbless Flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device", in IEEE International Electron Devices Meeting (IEDM' 08), pp. 1-4, Dec. 2008.
    • (2008) IEEE International Electron Devices Meeting (IEDM' 08) , pp. 1-4
    • Komori, Y.1
  • 29
    • 33751024366 scopus 로고    scopus 로고
    • A new programming disturbance phenomenon in NAND flash memory by source/drain hot-electrons generated by GIDL current
    • 21st
    • J.-D. Lee et al., "A New Programming Disturbance Phenomenon in NAND Flash Memory By Source/Drain Hot-Electrons Generated By GIDL Current", Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st, pp. 31-33, 2006.
    • (2006) Non-volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006 , pp. 31-33
    • Lee, J.-D.1
  • 30
    • 34547918920 scopus 로고    scopus 로고
    • Scalable wordline shielding scheme using dummy cell beyond 40 nm NAND flash memory for eliminating abnormal disturb of edge memory cell
    • Online
    • K.-T. Park et al., "Scalable Wordline Shielding Scheme using Dummy Cell beyond 40 nm NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell", Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 2188-2192, 2007. [Online]. Available: http://jjap. ipap. jp/link?JJAP/46/2188
    • (2007) Japanese Journal of Applied Physics , vol.46 , Issue.4 B , pp. 2188-2192
    • Park, K.-T.1
  • 31
    • 0035506993 scopus 로고    scopus 로고
    • A dual-mode NAND Flash memory: 1-Gb multilevel and highperformance 512-Mb single-level modes
    • Nov.
    • T. Cho et al., "A dual-mode NAND Flash memory: 1-Gb multilevel and highperformance 512-Mb single-level modes", IEEE Journal of Solid-State Circuits, vol. 36, no. 11, pp. 1700-1706, Nov. 2001.
    • (2001) IEEE Journal of Solid-state Circuits , vol.36 , Issue.11 , pp. 1700-1706
    • Cho, T.1
  • 33
    • 0242551720 scopus 로고    scopus 로고
    • A 90-nm CMOS 1.8-V 2-Gb NAND Flash memory for mass storage applications
    • Nov.
    • J. Lee et al., "A 90-nm CMOS 1.8-V 2-Gb NAND Flash memory for mass storage applications", IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1934-1942, Nov. 2003.
    • (2003) IEEE Journal of Solid-state Circuits , vol.38 , Issue.11 , pp. 1934-1942
    • Lee, J.1
  • 34
    • 0031274013 scopus 로고    scopus 로고
    • A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND Flash memory technology
    • Nov.
    • T.-S. Jung et al., "A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND Flash memory technology", IEEE Journal of Solid-State Circuits, vol. 32, no. 11, pp. 1748-1757, Nov. 1997.
    • (1997) IEEE Journal of Solid-state Circuits , vol.32 , Issue.11 , pp. 1748-1757
    • Jung, T.-S.1
  • 35
    • 0034179167 scopus 로고    scopus 로고
    • A source-line programming scheme for low-voltage operation NAND Flash memories
    • May
    • K. Takeuchi, S. Satoh, K. Imamiya, and K. Sakui, "A source-line programming scheme for low-voltage operation NAND Flash memories", IEEE Journal of Solid-State Circuits, vol. 35, no. 5, pp. 672-681, May 2000.
    • (2000) IEEE Journal of Solid-state Circuits , vol.35 , Issue.5 , pp. 672-681
    • Takeuchi, K.1    Satoh, S.2    Imamiya, K.3    Sakui, K.4
  • 37
    • 0030291637 scopus 로고    scopus 로고
    • A 117-mm2 3.3-V only 128-Mb multilevel NAND Flash memory for mass storage applications
    • Nov.
    • T.-S. Jung et al., "A 117-mm2 3.3-V only 128-Mb multilevel NAND Flash memory for mass storage applications", IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1575-1583, Nov. 1996.
    • (1996) IEEE Journal of Solid-state Circuits , vol.31 , Issue.11 , pp. 1575-1583
    • Jung, T.-S.1
  • 39
    • 48649096339 scopus 로고    scopus 로고
    • A new self-boosting phenomenon by soure/drain depletion cut-off in NAND flash memory
    • Aug.
    • D. Oh et al., "A New Self-Boosting Phenomenon by Soure/Drain Depletion Cut-off in NAND Flash Memory", in Proceedings of 22nd IEEE Non-Volatile Semiconductor Memory Workshop, pp. 39-41, Aug. 2007.
    • (2007) Proceedings of 22nd IEEE Non-volatile Semiconductor Memory Workshop , pp. 39-41
    • Oh, D.1
  • 40
    • 84892110563 scopus 로고    scopus 로고
    • Method of programming non-volatile semiconductor memory device
    • August, Online
    • J.-y. Jeong, J.-s. Yeom, and S.-s. Lee, "Method of programming non-volatile semiconductor memory device", Patent 20 020 118 569, August, 2002. [Online]. Available: http://www.freepatentsonline.com/y2002/0118569.html
    • (2002) Patent 20 020 118 569
    • Jeong, J.-.1    Yeom, J.-.2    Lee, S.-.3
  • 41
    • 84892106703 scopus 로고    scopus 로고
    • Source side self boosting technique for non-volatile memory
    • February, Online
    • J. W. Lutze, J. Chen, Y. Li, and M. Higashitani, "Source side self boosting technique for non-volatile memory", Patent 6 859 397, February, 2005. [Online]. Available: http://www.freepatentsonline.com/6859397.html
    • (2005) Patent 6 859 397
    • Lutze, J.W.1    Chen, J.2    Li, Y.3    Higashitani, M.4
  • 45
    • 0043175221 scopus 로고    scopus 로고
    • Statistical simulation of leakage currents in MOS and Flash memory devices with a new multiphonon trap-assisted tunneling model
    • May
    • L. Larcher, "Statistical simulation of leakage currents in MOS and Flash memory devices with a new multiphonon trap-assisted tunneling model", IEEE Transactions on Electron Devices, vol. 50, no. 5, pp. 1246-1253, May 2003.
    • (2003) IEEE Transactions on Electron Devices , vol.50 , Issue.5 , pp. 1246-1253
    • Larcher, L.1
  • 47
    • 37549006492 scopus 로고    scopus 로고
    • The impact of random telegraph signals on the scaling of multilevel flash memories
    • H. Kurata et al., "The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories", Symposium on VLSI Circuits, 2006. Digest of Technical Papers, pp. 112-113, 2006.
    • (2006) Symposium on VLSI Circuits, 2006. Digest of Technical Papers , pp. 112-113
    • Kurata, H.1
  • 48
    • 46149101236 scopus 로고    scopus 로고
    • Anomalously large threshold voltage fluctuation by complex random telegraph signal in floating gate flash memory
    • Dec.
    • N. Tega et al., "Anomalously Large Threshold Voltage Fluctuation by Complex Random Telegraph Signal in Floating Gate Flash Memory", in International Electron Devices Meeting, 2006. IEDM'06, pp. 1-4, Dec. 2006.
    • (2006) International Electron Devices Meeting, 2006. IEDM'06 , pp. 1-4
    • Tega, N.1
  • 49
    • 37749015265 scopus 로고    scopus 로고
    • Statistical model for random telegraph noise in flash memories
    • Jan.
    • C. M. Compagnoni et al., "Statistical Model for Random Telegraph Noise in Flash Memories", IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 388-395, Jan. 2008.
    • (2008) IEEE Transactions on Electron Devices , vol.55 , Issue.1 , pp. 388-395
    • Compagnoni, C.M.1
  • 50
    • 0026137736 scopus 로고
    • A 4 Mb NAND EEPROM with tight programmed Vt distribution
    • Apr.
    • M. Momodomi et al., "A 4 Mb NAND EEPROM with tight programmed Vt distribution", IEEE Journal of Solid-State Circuits, vol. 26, no. 4, pp. 492-496, Apr. 1991.
    • (1991) IEEE Journal of Solid-state Circuits , vol.26 , Issue.4 , pp. 492-496
    • Momodomi, M.1
  • 51
    • 84892016174 scopus 로고    scopus 로고
    • High density non-volatile Flash memory without adverse effects of electric field coupling between adjacent floating gates
    • Online
    • J. Chen and Y. Fong, "High density non-volatile Flash memory without adverse effects of electric field coupling between adjacent floating gates", US Patent 5 867 429, February, 1999. [Online]. Available: http://www.freepatentsonline.com/5867429.html
    • (1999) US Patent 5 867 429, February
    • Chen, J.1    Fong, Y.2
  • 52
    • 0036575326 scopus 로고    scopus 로고
    • Effects of floating-gate interference on NAND Flash memory cell operation
    • May
    • J.-D. Lee, S.-H. Hur, and J.-D. Choi, "Effects of floating-gate interference on NAND Flash memory cell operation", IEE Electron Device Letters, vol. 23, no. 5, pp. 264-266, May 2002.
    • (2002) IEE Electron Device Letters , vol.23 , Issue.5 , pp. 264-266
    • Lee, J.-D.1    Hur, S.-H.2    Choi, J.-D.3
  • 53
    • 28044473172 scopus 로고    scopus 로고
    • 3D Simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories
    • A. Ghetti, L. Bortesi, and L. Vendrame, "3D Simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories", Solid-State Electronics, vol. 49, no. 11, pp. 1805-1812, 2005.
    • (2005) Solid-state Electronics , vol.49 , Issue.11 , pp. 1805-1812
    • Ghetti, A.1    Bortesi, L.2    Vendrame, L.3
  • 55
    • 46049089836 scopus 로고    scopus 로고
    • Improving the cell characteristics using low-k gate spacer in 1Gb NAND flash memory
    • Dec.
    • D. Kang et al., "Improving the Cell Characteristics Using Low-k Gate Spacer in 1Gb NAND Flash Memory", in International Electron Devices Meeting, 2006. IEDM'06, pp. 1-4, Dec. 2006.
    • (2006) International Electron Devices Meeting, 2006. IEDM'06 , pp. 1-4
    • Kang, D.1
  • 56
    • 39749149108 scopus 로고    scopus 로고
    • A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond
    • June
    • K.-T. Park, "A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond", IEEE Symposium on VLSI Circuits, pp. 188-189, June 2007.
    • (2007) IEEE Symposium on VLSI Circuits , pp. 188-189
    • Park, K.-T.1
  • 57
    • 39749099420 scopus 로고    scopus 로고
    • A 70nm 16Gb 16-level-cell NAND flash memory
    • June
    • N. Shibata et al., "A 70nm 16Gb 16-level-cell NAND Flash Memory", IEEE Symposium on VLSI Circuits, pp. 190-191, June 2007.
    • (2007) IEEE Symposium on VLSI Circuits , pp. 190-191
    • Shibata, N.1
  • 58
    • 0033116234 scopus 로고    scopus 로고
    • Single-electron memory for giga-to-tera bit storage
    • Apr.
    • K. Yano et al., "Single-electron memory for giga-to-tera bit storage", Proceedings of the IEEE, vol. 87, no. 4, pp. 633-651, Apr. 1999.
    • (1999) Proceedings of the IEEE , vol.87 , Issue.4 , pp. 633-651
    • Yano, K.1
  • 60
    • 34548805944 scopus 로고    scopus 로고
    • Degradation of floating-gate memory reliability by few electron phenomena
    • Oct.
    • G. Molas et al., "Degradation of floating-gate memory reliability by few electron phenomena", IEEE Transactions on Electron Devices, vol. 53, no. 10, pp. 2610-2619, Oct. 2006.
    • (2006) IEEE Transactions on Electron Devices , vol.53 , Issue.10 , pp. 2610-2619
    • Molas, G.1
  • 61
    • 50249132614 scopus 로고    scopus 로고
    • First evidence for injection statistics accuracy limitations in NAND Flash constant-current Fowler-Nordheim programming
    • Dec.
    • C. Compagnoni et al., "First evidence for injection statistics accuracy limitations in NAND Flash constant-current Fowler-Nordheim programming", in IEEE International Electron Devices Meeting, 2007. IEDM'07, pp. 165-168, Dec. 2007.
    • (2007) IEEE International Electron Devices Meeting, 2007. IEDM'07 , pp. 165-168
    • Compagnoni, C.1
  • 62
    • 56549115798 scopus 로고    scopus 로고
    • Analytical model for the electron-injection statistics during programming of nanoscale NAND Flash memories
    • Nov.
    • C. Compagnoni et al., "Analytical model for the electron-injection statistics during programming of nanoscale NAND Flash memories", IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3192-3199, Nov. 2008.
    • (2008) IEEE Transactions on Electron Devices , vol.55 , Issue.11 , pp. 3192-3199
    • Compagnoni, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.