A 70nm 16Gb 16-level-cell NAND flash memory

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 190-191

  Shibata, Noboru ^a   Maejima, Hiroshi ^a   Isobe, Katsuaki ^a   Iwasa, Kiyoaki ^a   Nakagawa, Michio ^a   Fujiu, Masaki ^a   Shimizu, Takahiro ^a   Honma, Mitsuaki ^a   Hoshi, Satoru ^a   Kawaai, Toshimasa ^a   Kanebako, Kazunori ^a   Yoshikawa, Susumu ^a   Tabata, Hideyuki ^a   Inoue, Atsushi ^a   Takahashi, Toshiyuki ^a   Shano, Toshifumi ^a   Komatsu, Yukio ^a   Nagaba, Katsushi ^a   Kosakai, Mitsuhiko ^a   Motohashi, Noriaki ^a   Kanazawa, Kazuhisa ^a   Imamiya, Kenichi ^a   Nakai, Hiroto ^a   more..

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FLASH MEMORY; PROGRAMMING THEORY;

BIT DENSITY; DESIGN RULES;

NAND CIRCUITS;

EID: 39749099420     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342710     Document Type: Conference Paper

References (3)

1. T. Hara, et al., "A 146mm2 8Gb NAND Flash Memory with 70nm CMOS Technology", ISSCC Digest of Technical Papers, pp. 4445, Feb. 2005
2. T Cho, et al., "A 3.3V 1Gb Multi-Level NAND Flash Memory with Non-Uniform Threshold Voltage Distribution", ISSCC Digest of Technical Papers, pp. 28-29, Feb. 2001
3. Suh,KD.,et al., "A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse rtogramming Scheme", IEEE Journal of Solid-State Circuits Vol. 30, No. 11, pp. 1149-1156, Nov. 1995.