Investigation of the low-field leakage through high-k interpoly dielectric stacks and its impact on nonvolatile memory data retention

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Govoreanu, B ^a   Wellekens, D ^a   Haspeslagh, L ^a   De Vos, J ^a   Van Houdt, J ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES;

DATA-RETENTION; FLOATING GATE; INTER-POLY DIELECTRICS; NON-VOLATILE MEMORIES; TRAP ASSISTED TUNNELLING; TRAP DISTRIBUTIONS; TRAP PARAMETERS;

DATA STORAGE EQUIPMENT;

EID: 46049118849     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346818     Document Type: Conference Paper

References (6)

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2. M. Herrmann, and A. Schenk: "Field and high-temperature dependence of the long term charge loss in erasable programmable read only memories: measurements and modeling", J. Appl. Phys, vol. 77, pp. 4522-4540, 1995.
3. J. De Vos, L. Haspeslagh, M. Demand, K. Devriendt, D. Wellekens, S. Beckx, and J. Van Houdt : "A scalable Stacked Gate NOR/NAND Flash Technology compatible with high-k and metal gates for sub 45 nm generations", Proc. ICICDT, pp. 21-24, 2006.
4. 3 based Flash interpoly dielectrics: a comparative retention study", Proc. ESSDERC, 2006 (in press).
5. S.T. Wang: "Charge retention of floating-gate transistors under applied bias conditions", IEEE Trans. El Dev, vol. 27, pp. 297-299, 1980.
6. 3", Appl Phys. Lett. vol. 81, pp. 1678-1680, 2002.