Technology for sub-50nm DRAM and NAND flash manufacturing

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 323-326

  Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

PRODUCTION ENGINEERING; PROM; TECHNOLOGICAL FORECASTING; TRANSISTORS;

LOGIC ARRAYS; MEMORY ARRAYS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 33847707730     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Kinam Kim et al., "Memory technologies in Nano-era:Challenges and Opportunities,"(invited) ISSCC Dig. Tech. Papers, pp. 576-577, 2005.
2. Kinam Kim et al., "DRAM technology perspective for Gigabit era,"(invited) IEEE Trans. Electron Dev. 45, pp.598-608, 1998.
3. Y. Park et al., "COB stack cell technology beyond 100nm technology node," Technical Digest IEDM, pp.391, 2001.
4. D.H. Kim et al., "A Mechanically Enhanced Storage node for virtually unlimited Height(MESH) capacitor aiming at sub 70nm DRAM," Technical Digest IEDM, pp.69-72, 2004
5. J. Y. Kim et al., "The Breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88nm feature size and beyond," VLSI Technical Digest, pp.11-12, 2003.
6. J. Y. Kim et al., "S-RCAT (Sphere-shaped-Recess-Channel- Array-Transistor) Technology for 70nm DRAM feature size and beyond," VLSI Technical Digest, pp.34-35, 2005.
7. D. G. Park et al., "3-dimensional-CMOS transistor to overcome scaling limits," Proceedings of ICSICT, pp.35-38, 2004.
8. Y. S. Kim et al., "Local-Damascene-FinFET DRAM integration with p+ doped polysilicon gate technology for sub-60nm device generation," will be published in Technical Digest IEDM, 2005.
9. K.N. Kim et al., "The future prospect of non-volatile memory" Technical Digest VLSI-TSA, pp.88-94, 2005.
10. Y. Shin et al., "Non-volatile memory technologies for beyond 2010" Technical Digest VLSI, 2005.
11. P. Xuan et al., "FinFET SONOS falsh memory for embedded applications," IEDM Technical Digest, pp 609-612, 2003.
12. J.D.Choi et al., "A novel booster plate technology in high density NAND flash memories for voltage scaling-down and zero program disturbance," Technical Digest VLSI, pp. 238-239, 1996
13. Y.C.Shin et al., "A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs" will be published in Technical Digest IEDM, 2005.