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Volumn , Issue , 2008, Pages

Novel model for cell - System interaction (MCSI) in NAND flash

Author keywords

[No Author keywords available]

Indexed keywords

EFFICIENT ALGORITHMS; EXPERIMENTAL DATUM; FUTURE TECHNOLOGIES; INTRINSIC NOISE; MEMORY CELLS; MEMORY SYSTEMS; MEMORY TRANSISTORS; NAND FLASH MEMORIES; NAND FLASHES; PROGRAM OPERATIONS; STEP PULSE; SYSTEM INTERACTIONS;

EID: 64549153942     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796826     Document Type: Conference Paper
Times cited : (17)

References (7)
  • 1
    • 37549006492 scopus 로고    scopus 로고
    • The impact of random telegraph signals on the scaling of multilevel flash memories
    • H. Kurata et al. "The impact of random telegraph signals on the scaling of multilevel flash memories" VLSI Circuits Tech Digest, pp. 112-113, 2006.
    • (2006) VLSI Circuits Tech Digest , pp. 112-113
    • Kurata, H.1
  • 2
    • 50249132614 scopus 로고    scopus 로고
    • First evidence for injection statistics accuracy limitations in NAND flash constant-current Fowler-Nordheim programming
    • C. M. Compagnoni et al. "First evidence for injection statistics accuracy limitations in NAND flash constant-current Fowler-Nordheim programming" IEDM Tech Digest, pp. 165-168, 2007.
    • (2007) IEDM Tech Digest , pp. 165-168
    • Compagnoni, C.M.1
  • 3
    • 46049089836 scopus 로고    scopus 로고
    • Improving the cell characteristics using low-k gate spacer in 1Gb NAND flash memory
    • D. Kang et al. "Improving the cell characteristics using low-k gate spacer in 1Gb NAND flash memory" IEDM Tech Digest, pp. 1001-1004, 2006.
    • (2006) IEDM Tech Digest , pp. 1001-1004
    • Kang, D.1
  • 4
    • 39749149108 scopus 로고    scopus 로고
    • A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond
    • K. T. Park et al. "A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond" VLSI Circuits Tech.Digest, pp. 188-189, 2007.
    • (2007) VLSI Circuits Tech.Digest , pp. 188-189
    • Park, K.T.1
  • 5
    • 0029251968 scopus 로고
    • A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
    • K. D. Suh et al. "A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme" ISSCC Tech Digest, pp. 128-129,350, 1995.
    • (1995) ISSCC Tech Digest , vol.350 , pp. 128-129
    • Suh, K.D.1
  • 6
    • 0031376620 scopus 로고    scopus 로고
    • A multi-page cell architecture for high-speed programming multi-level NAND flash memories
    • K. Takeuchi, T. Tanaka and T. Tanzawa "A multi-page cell architecture for high-speed programming multi-level NAND flash memories" VLSI Circuits Tech. Digest, pp. 67-68, 1997.
    • (1997) VLSI Circuits Tech. Digest , pp. 67-68
    • Takeuchi, K.1    Tanaka, T.2    Tanzawa, T.3
  • 7
    • 49549114895 scopus 로고    scopus 로고
    • A 34MB/s-program-throiighput 16Gb MLC NAND with all-bitline architecture in 56nm
    • R. Cernea et al. "A 34MB/s-program-throiighput 16Gb MLC NAND with all-bitline architecture in 56nm" ISSCC Tech Digest, pp. 420-421,624, 2008.
    • (2008) ISSCC Tech Digest , vol.624 , pp. 420-421
    • Cernea, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.