A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 188-189

  Park, Ki Tae ^a   Kang, Myounggon ^a   Kim, Doogon ^a   Hwang, Soonwook ^a   Lee, Yeong Taek ^a   Kim, Changhyun ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; FLASH MEMORY; SCALING LAWS;

CRITICAL SCALING BARRIER; FLOATING GATE; PAGE ARCHITECTURE;

NAND CIRCUITS;

EID: 39749149108     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342709     Document Type: Conference Paper

References (5)

1. K. Kim, NVSMW, pp.9-11, 2006
2. T-H Clio, et al., JSSC. vol.36, no. 11, pp. 1700-1706, 2001
3. S. Lee, et al., ISSCC, pp.52-53, 2004
4. T. Hura, et al., ISSCC, pp.44-45, 2005
5. T. Tanaka, et al., JSSC, vol.29, no.11, pp.1366-1373, 1994