Efficient scrub mechanisms for error-prone emerging memories

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2012, Pages 15-26

  Awasthi, Manu ^a,c   Shevgoor, Manjunath ^a   Sudan, Kshitij ^a   Rajendran, Bipin ^b   Balasubramonian, Rajeev ^a   Srinivasan, Viii ^b  

^a UNIVERSITY OF UTAH   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c MICRON TECHNOLOGY INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE COMMUNITY; DRAM MEMORIES; ECC CODES; ERROR PRONES; ERROR TOLERANCE; FLASH TECHNOLOGY; HIGH DENSITY; MEMORY CELL; MULTILEVEL CELL; NEW SOURCES; NONVOLATILITY; SCALING LIMITS; SINGLE-BIT; SOFT ERROR; SOFT ERROR RATE;

ALGORITHMS; COMPUTER ARCHITECTURE; ERROR CORRECTION; MICROPROCESSOR CHIPS; SUPERCOMPUTERS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84860323239     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2012.6168941     Document Type: Conference Paper

References (47)

1. Multilevel Phase Change Memories. http://www.thinfilmproducts.umicore. com/feature.asp?page=art6.
2. Research Needs for Memory Technologies. Technical report, Semiconductor Research Corporation (SRC), 2011. www.src.org/program/grc/ds/research-needs/ 2011/memory.pdf.
3. C. Benia et al. The PARSEC Benchmark Suite: Characterization and Architectural Implications. Technical report, Princeton University, 2008.
4. M. Boniardi, D. Ielmini, S. Lavizzari, A. Lacaita, A. Redaelli, and A. Pirovano. Statistical and scaling behavior of structural relaxation effects in phase-change memory (PCM) devices. 2009.
5. G. W. Burr, M. J. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, L. A. Lastras, A. Padilla, B. Rajendran, S. Raoux, and R. S. Shenoy. Phase Change Memory Technology, 2010. http://arxiv.org/abs/1001.1164v1.
6. S. Cho and H. Lee. Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy, and Endurance. In Proceedings of MICRO, 2009.
7. W. Gao and S. Simmons. A study on the VLSI implementation of ECC for embedded DRAM. In Proceedings of IEEE CCECE, 2003.
8. L. Goux, T. Gille, D. Castro, G. Hurkx, J. Lisoni, R. Delhougne, D. Gravesteijn, K. De Meyer, K. Attenborough, and D. Wouters. Transient Characteristics of the Reset Programming of a Phase-Change Line Cell and the Effect of the Reset Parameters on the Obtained State. Electron Devices, IEEE Transactions on, 56(7), 2009.
9. L. Goux, D. Tio Castro, G. Hurkx, J. Lisoni, R. Delhougne, D. Gravesteijn, K. Attenborough, and D. Wouters. Degradation of the Reset Switching During Endurance Testing of a Phase-Change Line Cell. Electron Devices, IEEE Transactions on, 56(2), 2009.
10. R. Hamming. Error detecting and error correcting codes. Bell System Technical Journal, 1950.
11. Y. Hwang, C. Um, J. Lee, C.Wei, H. Oh, G. Jeong, H. Jeong, C. Kim, and C. Chung. MLC PRAM with SLC write-speed and robust read scheme. In Proceedings of Symposium on VLSI Technology, 2010.
12. D. Ielmini, M. Boniardi, A. Lacaita, A. Redaelli, and A. Pirovano. Unified mechanisms for structural relaxation and crystallization in phase-change memory devices. Microelectronic Engineering, 86(7-9):1942-1945, 2009. INFOS 2009.
13. D. Ielmini, D. Sharma, S. Lavizzari, and A. Lacaita. Reliability Impact of Chalcogenide-Structure Relaxation in Phase-Change Memory (PCM) Cells ;Part I: Experimental Study. Electron Devices, IEEE Transactions on, 56(5), may 2009.
14. E. Ipek, J. Condit, E. Nightingale, D. Burger, and T. Moscibroda. Dynamically Replicated Memory : Building Reliable Systems from nanoscale Resistive Memories. In Proceedings of ASPLOS, 2010.
15. B. Jacob, S. W. Ng, and D. T. Wang. Memory Systems - Cache, DRAM, Disk. Elsevier, 2008.
16. C.-W. Jeong, D.-H. kang, H.-J. Kim, S.-P. Ko, and D.-W. Lim. Multiple Level Cell Phase-Change Memory Devices Having Controlled Resistance Drift Parameter, Memory Systems Employing Such Devices and Methods of Reading Memory Devices, 2008. United States Patent Application, Number US 2008/0316804 A1 .
17. S. Kang, W. Y. Cho, B.-H. Cho, K.-J. Lee, C.-S. Lee, H.-R. Oh, B.-G. Choi, Q. Wang, H.-J. Kim, M.-H. Park, Y. H. Ro, S. Kim, C.-D. Ha, K.-S. Kim, Y.-R. Kim, D.-E. Kim, C.-K. Kwak, H.-G. Byun, G. Jeong, H. Jeong, K. Kim, and Y. Shin. A 0.1- μm 1.8-V 256-Mb Phase-Change Random AccessMemory (PRAM)With 66-MHz Synchronous Burst-Read Operation. Solid-State Circuits, IEEE Journal of, 42(1), jan. 2007.
18. A. Kostylev and W. Czubatyj. Method of Eliminating Drift in Phase-Change Memory, 2004. United States Patent Application, Number US 2004/0228159 A1 .
19. S. K. Lai. Flash memories: Successes and challenges. IBM Journal of Research and Development, 52(4.5), 2008.
20. B. Lee, E. Ipek, O.Mutlu, and D. Burger. Architecting Phase Change Memory as a Scalable DRAM Alternative. In Proceedings of ISCA, 2009.
21. J.-T. Lin, Y.-B. Liao,M.-H. Chiang, I.-H. Chiu, C.-L. Lin,W.-C. Hsu, P.-C. Chiang, S.-S. Sheu, Y.-Y. Hsu, W.-H. Liu, K.-L. Su, M.-J. Kao, and M.-J. Tsai. Design optimization in write speed of multi-level cell application for phase change memory. In Intl. Conf. of Electron Devices and Solid-State Circuits, 2009.
22. J.-T. Lin, Y.-B. Liao, M.-H. Chiang, and W.-C. Hsu. Operation of Multi-Level Phase Change Memory Using Various Programming Techniques. In Proceedings of ICICDT, 2009.
23. W. Mueller, G. Aichmayr, W. Bergner, E. Erben, T. Hecht, C. Kapteyn, A. Kersch, S. Kudelka, F. Lau, J. Luetzen, A. Orth, J. Nuetzel, T. Schloesser, A. Scholz, U. Schroeder, A. Sieck, A. Spitzer, M. Strasser, P.-F. Wang, S. Wege, and R. Weis. Challenges for the DRAM cell scaling to 40nm. 2005.
24. T. Nirschl, J. Phipp, T. Happ, G. Burr, B. Rajendran, M.-H. Lee, A. Schrott, M. Yang, M. Breitwisch, C.-F. Chen, E. Joseph, M. Lamorey, R. Cheek, S.-H. Chen, S. Zaidi, S. Raoux, Y. Chen, Y. Zhu, R. Bergmann, H.-L. Lung, and C. Lam. Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory. 2007.
25. A. Pantazi, A. Sebastian, N. Papandreou, M. J. Breitwisch, C. Lam, H. Pozidis, and E. Eleftheriou. Multilevel Phase-Change Memory Modeling and Experimental Characterization. In Proceedings of EP-COS, 2009.
26. N. Papandreou, H. Pozidis, T. Mittelholzer, G. Close, M. Breitwisch, C. Lam, and E. Eleftheriou. Drift-tolerant multilevel phase-change memory. In Proceedings of International Memory Workshop (IMW), 2011.
27. S. Paul, F. Cai, X. Zhang, and S. Bhunia. Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache. IEEE Transactions on Computers, 99, 2010.
28. A. Pirovano, A. Lacaita, F. Pellizzer, S. Kostylev, A. Benvenuti, and R. Bez. Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials. IEEE Transactions on Electron Devices, 51(5), may 2004.
29. M. Qureshi, M. Franceschini, and L. Lastras. Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing. In Proceedings of HPCA, 2010.
30. M. Qureshi, M. Franceschini, L. Lastras-Montano, and J. Karidis. Morphable Memory System: A Robust Architecture for Exploiting Multi-Level Phase Change Memory. In Proceedings of ISCA, 2010.
31. M. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali. Enhancing Lifetime and Security of PCM-Based Main Memory with Start-Gap Wear Leveling. In Proceedings of MICRO, 2009.
32. M. Qureshi, V. Srinivasan, and J. Rivers. Scalable High Performance Main Memory System Using Phase-Change Memory Technology. In Proceedings of ISCA, 2009.
33. A. Redaelli, A. Pirovano, A. Locatelli, and F. Pellizzer. Numerical Implementation of Low Field Resistance Drift for Phase Change Memory Simulations. In Non-Volatile Semiconductor Memory Workshop, 2008.
34. S. Kostylev and T. Lowrey. Drift of Programmed Resistance In Electrical Phase Change Memory Devices, 2008.
35. S. Schechter, G. Loh, K. Strauss, and D. Burger. Use ECP, not ECC, for hard Failures in Resistive Memories. In Proceedings of ISCA, 2010.
36. B. Schroeder, E. Pinheiro, and W.Weber. DRAM Errors in the Wild: A Large-Scale Field Study. In Proceedings of SIGMETRICS, 2009.
37. N. Seong, D. Woo, V. Srinivasan, J. Rivers, and H. Lee. SAFER: Stuck-At-Fault Error Recovery for Memories. In Proceedings of MICRO, 2010.
38. A. Udipi, N. Muralimanohar, R. Balasubramonian, A. Davis, and N. Jouppi. Combining Memory and a Controller with Photonics through 3D-Stacking to Enable Scalable and Energy-Efficient Systems. In Proceedings of ISCA, 2011.
39. A. N. Udipi et al. Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores. In Proceedings of ISCA, 2010.
40. C. Wilkerson, A. Alameldeen, Z. Chishti, W. Wu, D. Somasekhar, and S.-L. Lu. Reducing Cache Power with Low-Cost,Multi-Bit Error Correcting Codes. In Proceedings of ISCA, 2010.
41. W. Xu, J. Liu, and T. Zhang. Data Manipulation Techniques to Reduce Phase Change Memory Write Energy. In Proceedings of ISLPED, 2009.
42. W. Xu and T. Zhang. A time-aware fault tolerance scheme to improve reliability of multilevel phase-change memory in presence of significant resistance drift. IEEE Transactions on VLSI Systems, PP(99), 2010.
43. W. Xu and T. Zhang. Using Time-Aware Memory Sensing to Address Resistance Drift Issue in Multi-Level Phase Change Memory. In Proceedings of ISQED, 2010.
44. D. Yoon and M. Erez. Virtualized and Flexible ECC for Main Memory. In Proceedings of ASPLOS, 2010.
45. D.-H. Yoon, N.Muralimanohar, J. Chang, P. Ranganathan, N. Jouppi, and M. Erez. FREE-p: Protecting Non-Volatile Memory against both Hard and Soft Errors. In Proceedings of HPCA, 2011.
46. W. Zhang and T. Li. Helmet: A Resistance Drift Resilient Architecture for Multi-level Cell Phase Change Memory System. In Proceedings of DSN, 2011.
47. P. Zhou, B. Zhao, J. Yang, and Y. Zhang. A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology. In Proceedings of ISCA, 2009.