Rethinking DRAM design and organization for energy-constrained multi-cores

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2010, Pages 175-186

  Udipi, Aniruddha N ^a   Muralimanohar, Naveen ^b   Chatterjee, Niladrish ^a   Balasubramonian, Rajeev ^a   Davis, Al ^a   Jouppi, Norman P ^b  

^a UNIVERSITY OF UTAH   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

Chipkill; DRAM architecture; Energy efficiency; Locality; Subarrays

Indexed keywords

AREA PENALTY; BIT METRIC; BITLINES; CHECKSUM; DESIGN DECISIONS; DESIGN FLOWS; DRAM CHIPS; DRAM DESIGN; ENERGY CONSUMPTION; ENERGY-CONSTRAINED; HIGH ENERGY; MEMORY ACCESS; MEMORY ACCESS TIME; MEMORY CONTROLLER; MEMORY SYSTEMS; MEMORY TECHNOLOGY; MICRO ARCHITECTURES; MODERN TECHNOLOGIES; MULTI-CORE SYSTEMS; PERFORMANCE IMPROVEMENTS; PERFORMANCE PENALTIES; PROPOSED ARCHITECTURES; PURCHASE COST; QUEUING DELAY; SINGLE CHIPS; STORAGE OVERHEAD; SUB-ARRAYS; SUBARRAY;

CHEMICAL ACTIVATION; COMPUTER ARCHITECTURE; COMPUTERS; DESIGN; ERROR DETECTION; FAULT DETECTION; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; INNOVATION; MICROPROCESSOR CHIPS; OPERATING COSTS; QUALITY ASSURANCE; QUEUEING NETWORKS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 77954989143     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1815961.1815983     Document Type: Conference Paper

References (56)

1. CACTI: An Integrated Cache and Memory Access Time, Cycle Time, Area, Leakage, and Dynamic Power Model. http://www.hpl.hp.com/research/cacti/.
2. HP Advanced Memory Protection Technologies - Technology Brief. http://www.hp.com.
3. Micron System Power Calculator. http://www.micron.com/support/part info/powercalc.
4. STREAM - Sustainable Memory Bandwidth in High Performance Computers. http://www.cs.virginia.edu/stream/.
5. Virtutech Simics Full System Simulator. http://www.virtutech.com.
6. M. Abbott et al. Durable Memory RS/6000 System Design. In Proceedings of International Symposium on Fault-Tolerant Computing, 1994.
7. J. Ahn, J. Leverich, R. S. Schreiber, and N. Jouppi. Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs. IEEE Computer Architecture Letters, vol.7(1), 2008.
8. J. H. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber. Future Scaling of Processor-Memory Interfaces. In Proceedings of SC, 2009.
9. D. Bailey et al. The NAS Parallel Benchmarks. International Journal of Supercomputer Applications, 5(3):63-73, Fall 1991.
10. L. Barroso. The Price of Performance. Queue, 3(7):48-53, 2005.
11. L. Barroso and U. Holzle. The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines. Morgan & Claypool, 2009.
12. S. Beamer et al. Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics. In Proceedings of ISCA, 2010.
13. C. Benia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. Technical report, Department of Computer Science, Princeton University, 2008.
14. P. Burns et al. Dynamic Tracking of Page Miss Ratio Curve for Memory Management. In Proceedings of ASPLOS, 2004.
15. V. Cuppu and B. Jacob. Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance. In Proceedings of ISCA, 2001.
16. V. Delaluz et al. DRAM Energy Management Using Software and Hardware Directed Power Mode Control. In Proceedings of HPCA, 2001.
17. V. Delaluz et al. Scheduler-based DRAM Energy Management. In Proceedings of DAC, 2002.
18. T. J. Dell. A Whitepaper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory. Technical report, IBM Microelectronics Division, 1997.
19. X. Fan, H. Zeng, and C. Ellis. Memory Controller Policies for DRAM Power Management. In Proceedings of ISLPED, 2001.
20. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Elsevier, 4th edition, 2007.
21. H. Huang, P. Pillai, and K. G. Shin. Design And Implementation Of Power-Aware Virtual Memory. In Proceedings Of The Annual Conference On Usenix Annual Technical Conference, 2003.
22. H. Huang, K. Shin, C. Lefurgy, and T. Keller. Improving Energy Efficiency by Making DRAM Less Randomly Accessed. In Proceedings of ISLPED, 2005.
23. I. Hur and C. Lin. A Comprehensive Approach to DRAM Power Management. In Proceedings of HPCA, 2008.
24. E. Ipek, O. Mutlu, J. Martinez, and R. Caruana. Self Optimizing Memory Controllers: A Reinforcement Learning Approach. In Proceedings of ISCA, 2008.
25. K. Itoh. VLSI Memory Chip Design. Springer, 2001.
26. ITRS. International Technology Roadmap for Semiconductors, 2007 Edition. http://www.itrs.net/Links/2007ITRS/Home2007.htm.
27. B. Jacob, S. W. Ng, and D. T. Wang. Memory Systems - Cache, DRAM, Disk. Elsevier, 2008.
28. M. Kumanoya et al. An Optimized Design for High-Performance Megabit DRAMs. Electronics and Communications in Japan, 72(8), 2007.
29. O. La. SDRAM having posted CAS function of JEDEC standard, 2002. United States Patent, Number 6483769.
30. A. Lebeck, X. Fan, H. Zeng, and C. Ellis. Power Aware Page Allocation. In Proceedings of ASPLOS, 2000.
31. C. Lee, O. Mutlu, V. Narasiman, and Y. Patt. Prefetch-Aware DRAM Controllers. In Proceedings of MICRO, 2008.
32. C. Lefurgy et al. Energy management for commercial servers. IEEE Computer, 36(2):39-48, 2003.
33. K. Lim et al. Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments. In Proceedings of ISCA, 2008.
34. K. Lim et al. Disaggregated Memory for Expansion and Sharing in Blade Servers. In Proceedings of ISCA, 2009.
35. D. Locklear. Chipkill Correct Memory Architecture. Technical report, Dell, 2000.
36. G. Loh. 3D-Stacked Memory Architectures for Multi-Core Processors. In Proceedings of ISCA, 2008.
37. D. Meisner, B. Gold, and T. Wenisch. PowerNap: Eliminating Server Idle Power. In Proceedings of ASPLOS, 2009.
38. Micron Technology Inc. Micron DDR2 SDRAM Part MT47H256M8, 2006.
39. N. Muralimanohar, R. Balasubramonian, and N. Jouppi. Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. In Proceedings of MICRO, 2007.
40. O. Mutlu and T. Moscibroda. Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. In Proceedings of MICRO, 2007.
41. O. Mutlu and T. Moscibroda. Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems. In Proceedings of ISCA, 2008.
42. U. Nawathe et al. An 8-Core 64-Thread 64b Power-Efficient SPARC SoC. In Proceedings of ISSCC, 2007.
43. V. Pandey, W. Jiang, Y. Zhou, and R. Bianchini. DMA-Aware Memory Energy Management. In Proceedings of HPCA, 2006.
44. B. Rogers et al. Scaling the Bandwidth Wall: Challenges in and Avenues for CMP Scaling. In Proceedings of ISCA, 2009.
45. V. Romanchenko. Quad-Core Opteron: Architecture and Roadmaps. http://www.digital-daily.com/cpu/quad core opteron.
46. B. Schroeder, E. Pinheiro, and W. Weber. DRAM Errors in the Wild: A Large-Scale Field Study. In Proceedings of SIGMETRICS, 2009.
47. K. Sudan, N. Chatterjee, D. Nellans, M. Awasthi, R. Balasubramonian, and A. Davis. Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement. In Proceedings of ASPLOS-XV, 2010.
48. R. Swinburne. Intel Core i7 - Nehalem Architecture Dive. http://www.bit-tech.net/hardware/2008/11/03/intel-core-i7-nehalem-architecture- dive/.
49. S. Thoziyoor, N. Muralimanohar, and N. Jouppi. CACTI 5.0. Technical report, HP Laboratories, 2007.
50. U.S. Environmental Protection Agency - Energy Star Program. Report To Congress on Server and Data Center Energy Efficiency - Public Law 109-431, 2007.
51. D. Vantrease et al. Corona: System Implications of Emerging Nanophotonic Technology. In Proceedings of ISCA, 2008.
52. D. Wang et al. DRAMsim: A Memory-System Simulator. In SIGARCH Computer Architecture News, volume 33, September 2005.
53. F. A. Ware and C. Hampel. Improving Power and Data Efficiency with Threaded Memory Modules. In Proceedings of ICCD, 2006.
54. D. Wentzlaff et al. On-Chip Interconnection Architecture of the Tile Processor. In IEEE Micro, volume 22, 2007.
55. D. Yoon and M. Erez. Virtualized and Flexible ECC for Main Memory. In Proceedings of ASPLOS, 2010.
56. H. Zheng et al. Mini-Rank: Adaptive DRAM Architecture For Improving Memory Power Efficiency. In Proceedings of MICRO, 2008.