Drift-tolerant multilevel phase-change memory

2011 3rd IEEE International Memory Workshop, IMW 2011

Volumn , Issue , 2011, Pages

  Papandreou, N ^a   Pozidis, H ^a   Mittelholzer, T ^a   Close, G F ^a   Breitwisch, M ^b   Lam, C ^b   Eleftheriou, E ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

4-LEVEL; CODEWORD; CODING TECHNIQUES; MEMORY TECHNOLOGY; MODULATION CODING; PHASE CHANGES; PROTOTYPE CHIP; RELATIVE ORDER; RESISTANCE LEVEL; ROOM TEMPERATURE; STOCHASTIC NATURE;

PHASE CHANGE MEMORY;

EID: 79960015315     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2011.5873231     Document Type: Article

References (7)

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7. N. Papandreou, H. Pozidis, A. Pantazi, A. Sebastian, M. Breitwisch, C. Lam, and E. Eleftheriou, "Programming algorithms for multilevel phase-change memory," in Proc. IEEE ISCAS, 2011.