SAFER: Stuck-at-fault error recovery for memories

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 115-124

  Seong, Nak Hee ^a   Woo, Dong Hyuk ^a,c   Srinivasan, Vijayalakshmi ^b   Rivers, Jude A ^b   Lee, Hsien Hsin S ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Multi bit error correction; Phase change memory; Reliability; Resistive memory; Stuck at fault recovery; Write endurance

Indexed keywords

CODING SCHEME; CORRECTION TECHNIQUES; DATA BLOCKS; EARLY FAILURE; EMERGING NON-VOLATILE MEMORIES; ERROR RECOVERY; ERROR RECOVERY SCHEMES; HARDWARE OVERHEADS; IN-CELL; KEY ATTRIBUTES; LIFETIME IMPROVEMENT; MEMORY TECHNOLOGY; MULTI-BIT ERROR; MULTI-BITS; NOVEL HARDWARE; PHYSICAL LIMITATIONS; RESISTIVE MEMORY; STUCK-AT FAULTS; TECHNOLOGY SCALING; TRANSIENT FAULTS; WRITE ENDURANCE;

COMBINATORIAL CIRCUITS; DURABILITY; ERROR CORRECTION; PHASE CHANGE MEMORY; RECOVERY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 79951719573     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.46     Document Type: Conference Paper

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