Dynamically replicated memory: Building reliable systems from nanoscale resistive memories

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2010, Pages 3-14

  Ipek, Engin ^a   Condit, Jeremy ^b   Nightingale, Edmund B ^b   Burger, Doug ^b   Moscibroda, Thomas ^b  

^a UNIVERSITY OF ROCHESTER   (United States)

^b MICROSOFT RESEARCH   (United States)

Author keywords

Phase change memory; Write endurance

Indexed keywords

CACHE HIERARCHIES; DEEP SUB-MICRON; ERROR-DETECTION TECHNIQUES; GRACEFUL DEGRADATION; MEMORY CONTROLLER; MEMORY PAGES; NANO SCALE; OPERATING SYSTEM INTERFACES; OPERATING SYSTEMS; PAGE TABLE; PROCESSOR CORES; RELIABLE SYSTEMS; TEM;

COMPUTER OPERATING SYSTEMS; DURABILITY; DYNAMIC RANDOM ACCESS STORAGE; ERROR DETECTION; LINGUISTICS; NANOTECHNOLOGY; PULSE CODE MODULATION;

PHASE CHANGE MEMORY;

EID: 77952268480     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1736020.1736023     Document Type: Conference Paper

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