A 0.1-μm 1.8-V 256-Mb Phase-change Random Access Memory (PRAM) with 66-MHz synchronous burst-read operation

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 1, 2007, Pages 210-216

  Kang, Sangbeom ^b   Cho, Woo Yeong ^b   Cho, Beak Hyung ^b   Lee, Kwang Jin ^b   Lee, Chang Soo ^b   Oh, Hyung Rok ^b   Choi, Byung Gil ^b   Wang, Qi ^b   Kim, Hye Jin ^b   Park, Mu Hui ^b   Ro, Yu Hwan ^b   Kim, Suyeon ^b   Ha, Choong Duk ^b   Kim, Ki Sung ^b   Kim, Young Ran ^b   Kim, Du Eung ^b   Kwak, Choong Keun ^b   Byun, Hyun Geun ^b   Jeong, Gitae ^b   Jeong, Hongsik ^b   Kim, Kinam ^a,b   Shin, Yunsueng ^b   more..

^a IEEE

^b SAMSUNG Electronics   (South Korea)

Author keywords

Burst read; Charge pump; Endurance; Phase change memory; Phase change random access memory (PRAM); Reset; Retention

Indexed keywords

BURST READ; CHARGE PUMP; PHASE CHANGE MEMORY; PHASE CHANGE RANDOM ACCESS MEMORY (PRAM); RESET; RETENTION;

DURABILITY; ELECTRIC CHARGE; ELECTRIC POTENTIAL; PHASE CONTROL; THROUGHPUT;

RANDOM ACCESS STORAGE;

EID: 33846204280     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.888349     Document Type: Article

References (9)

1. M. Gill, T. Lowrey, and J. Park, "Ovonic unified memory: A high performance nonvolatile memory technology for stand alone and embedded applications," in IEEE ISSCC Dig. Tech. Papers, 2002, p. 202.
2. Y. N. Hwang et al., "Full integration and reliability evaluation of phase-change RAM based on 0.24μm-CMOS technologies," in Symp. VLSI Technology Dig. Tech. Papers, 2003, pp. 173-174.
3. W. Y. Cho et al., "A 0.18 μm 3.0 V 64 Mb non-volatile phase-transition random access memory (PRAM)," in IEEE ISSCC Dig. Tech. Papers, 2004, p. 40.
4. F. Bedeschi et al., "An 8Mb demonstrator for high-density 1.8V phasechange memories," in Symp. VLSI Circuits Dig. Tech. Papers, 2004, pp. 442-445.
5. H. Oh et al., "Enhanced write performance of a 64 Mb phase-change random access memory," in IEEE ISSCC Dig. Tech. Papers, 2005, p. 48.
6. Y. Shin, "Non-volatile memory technologies for beyond 2010," in Symp. VLSI Circuits Dig. Tech. Papers, 2005, pp. 156-159.
7. J. Lee et al., "A 1.8 V 1 Gb NAND flash memory with 0.12 μm STI process technology," in IEEE ISSCC Dig. Tech. Papers, 2002, p. 104.
8. M. Taub et al., "A 90 nm 512 Mb 166 MHz multilevel cell flash memory with 1.5 MByte/s programming," in IEEE ISSCC Dig. Tech. Papers, 2005, p. 54.
9. S. Kang et al., "A 0.1 μm 1.8V 256Mb 66MHz synchronous burst PRAM," in IEEE ISSCC Dig. Tech. Papers, 2006, p. 140.