Data manipulation techniques to reduce phase change memory write energy

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2009, Pages 237-242

  Wei, Xu ^a   Jibang, Liu ^a   Tong, Zhang ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

Low power; Phase change memory

Indexed keywords

COMPUTER MEMORIES; DATA MANIPULATIONS; ENERGY CONSUMPTION; ENERGY SAVING; LOW POWER; MAIN MEMORY; MATHEMATICAL ANALYSIS; MEMORY TECHNOLOGY; PHASE CHANGE MEMORY CELLS;

COMPUTER SIMULATION; COMPUTERS; ENERGY CONSERVATION; LOW POWER ELECTRONICS; POWER ELECTRONICS;

PHASE CHANGE MEMORY;

EID: 70449728142     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1594233.1594290     Document Type: Conference Paper

References (12)

1. C.H. Lam, "The quest for the universal semiconductor memory," in Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits, Dec. 2005, pp. 327-331.
2. K. Kim and G. Jeong, "Memory technologies for sub-40nm node," in Proc. of IEEE International Electron Devices Meeting (IEDM), Dec. 2007, pp. 27-30.
3. F. Bedeschi et al., "A multi-level-cell bipolar-selected phase-change memory," in Proceedings of the IEEE International Solid-State Circuits Conference, Feb. 2008, pp. 428-625.
4. T. Nirschl et al., "Write strategies for 2 and 4-bit multi-level phase-change memory," in Proceedings of the IEEE International Electron Devices Meeting, Dec. 2007, pp. 461-464.
5. S. Kang et al., "A 0.1-μm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) with 66-MHz Synchronous Burst-Read Operation," Journal of Solid-State Circiuts, vol. 42, no. 1, pp. 210-218, Jan. 2007.
6. H. Oh et al., "Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory," Journal of Solid-State Circiuts, vol. 41, no. 1, pp. 122-126, Jan. 2006.
7. K. Osada et al., "Phase Change RAM Operated with 1.5-V CMOS as Low Cost Embedded Memory," in Proceedings of the IEEE Custom Integrated Circuits Conference, Sept. 2005, pp. 431-434.
8. G.W. Burr et al., "Overview of candidate device technologies for storage-class memory," IBM Journal of Research and Development, vol. 52, no. 4/5, pp. 449-464, July/Sept. 2008.
9. M.R. Stan and W.P. Burleson, "Bus-invert coding for low-power I/O," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, pp. 49-58, March 1995.
10. A.L. Lacaita, "Phase change memories: State-of-the-art, challenges and perspectives," Solid-State Electronics, vol. 50, no. 1, pp. 24-31, Jan. 2006.
11. M5, http://www.m5sim.org, 2009.
12. Standard Performance Evaluation Corporation, http://www.spec.org/, 2000/2006.