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Volumn 1, Issue , 2003, Pages 203-206

A Study on the VLSI Implementation of ECC for Embedded DRAM

Author keywords

DRAM; ECC circuitry; LUT; SEC DEC code; XOR tree

Indexed keywords

ALPHA PARTICLES; ARRAYS; COMPUTER SIMULATION; COSMIC RAYS; DYNAMIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; FAULT TOLERANT COMPUTER SYSTEMS; NEUTRONS; RANDOM ERRORS; ROM;

EID: 0141453662     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (20)

References (9)
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  • 2
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  • 4
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    • Error-correcting codes for semiconductor memory applications: A State-of-the Art Review
    • March
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    • Chen, C.L.1    Hsiao, M.Y.2
  • 5
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    • Fast, minimal decoding complexity, systematic (13,8) single-error-correcting codes for on-chip DRAM applications
    • March
    • A. Kazeminejad, "Fast, minimal decoding complexity, systematic (13,8) single-error-correcting codes for on-chip DRAM applications," Electronics Letters, vol. 37, no. 7, pp.438-440, March 2001.
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    • Kazeminejad, A.1
  • 6
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    • Design of a fault-tolerant three-dimensional dynamic random-access memory with onchip error-correcting Circuit
    • Dec.
    • P. Mazumder, "Design of a fault-tolerant three-dimensional dynamic random-access memory with onchip error-correcting Circuit," IEEE Transactions on Computers, vol. 42, no. 12, pp. 1453-1468, Dec. 1993.
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    • Mazumder, P.1
  • 7
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    • A class of error control codes for byte organized memory systems SbEC-(Sb+S)ED codes
    • Jan.
    • M. Hamada, and E. Fujiwara, "A class of error control codes for byte organized memory systems SbEC-(Sb+S)ED codes -," IEEE Transactions on Computers, vol. 46, no.1, pp. 106-109, Jan. 1997.
    • (1997) IEEE Transactions on Computers , vol.46 , Issue.1 , pp. 106-109
    • Hamada, M.1    Fujiwara, E.2
  • 8
    • 0014823837 scopus 로고
    • A class of optimal minimum odd-weight-column SEC_DED codes
    • July
    • M. Y. Hsiao, "A class of optimal minimum odd-weight-column SEC_DED codes," IBM J. Res. Develop., vol. 14, pp. 395-401, July 1970.
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  • 9
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    • (1991) IEEE Journal of Solid-state Circuits , vol.26 , Issue.10 , pp. 1449-1452
    • Fifield, J.A.1    Stapper, C.H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.