Design optimization in write speed of multi-level cell application for phase change memory

2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009

Volumn , Issue , 2009, Pages 525-528

  Lin, Jun Tin ^a   Liao, Yi Bo ^b   Chiang, Meng Hsueh ^a   Chiu, I Hsuan ^a   Lin, Chia Long ^a   Hsu, Wei Chou ^b   Chiang, Pei Chia ^c   Sheu, Shyh Shyuan ^c   Hsu, Yen Ya ^c   Liu, Wen Hsing ^c   Su, Keng Li ^c   Kao, Ming Jer ^c   Tsai, Ming Jinn ^c  

^a National Han University   (Taiwan)

^b NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^c Electronics and Opto Electronics Research Laboratories of Industrial Technology Research Institute   (Taiwan)

Author keywords

MLC; PCM; Phase change memory

Indexed keywords

DESIGN OPTIMIZATION; MLC; MULTILEVEL CELL; PCM MODEL; SIMULATION RESULT; WRITE SPEED;

OPTIMIZATION; PULSE CODE MODULATION; SOLID STATE DEVICES;

PHASE CHANGE MEMORY;

EID: 77949635075     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2009.5394196     Document Type: Conference Paper

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